What is the difference between an N-MOS FET and a tri-state buffer? [closed]

Question

Is an N-MOS FET an equivalent of a tri-state buffer, where the source is the input, the gate is the enable, and the drain is the output?

Answer 1

Let me address what they are first before answering your question. Technically, an N-channel MOSFET (NMOS) is not equivalent to a Tri-State buffer. The latter is more complex and is built using several MOSFETs (assuming we are talking about the CMOS version of tri-state buffer).

The following are the simplified models of an NMOS and a Tri-state buffer represented by switches just to convey the concepts across and to show their behavioral similarities and differences.

Both have an input and an output, but the tri-state buffer has a control input which enables/disables the output. For the models above, you give the inputs by clicking on the switches.

The NMOS is either connected to GND or disconnected from it. The Tri-state buffer is slightly more complex.

The name tri-state comes from its properties of having 3 stable states, namely, high output state, low output state, and high-impedance state. When the switch is connected to the +5V supply, its output will be driven to a high state*. When the switch is connected to the GND, its output will be driven to a low state*. When the enable switch is open, then its internal circuit is disconnected from the output terminal, so the output will neither be driven high nor low and therefore remains in high-impedance state (or Hi-Z or floating).

[* assuming the Enable switch is closed]

Here are 2 circuits using NMOS that you can play around with. By clicking on the switches, you will see the left circuit turning ON/OFF the red LED, but the LED of the circuit on the right will not light up no matter whether the switch is closed or open.

Here are 2 similar circuits using Tri-state buffers.

By clicking on the switches, you will see the left and right circuits turning ON/OFF their respective LEDs, except that they are opposite to one another. The table below summarizes the results.

Note that when the Enable switch is open, both LEDs remain OFF. This is because the output cannot be driven high or low no matter what input you give.

On the practical side, a tri-state buffer is only used for signaling and is never used for driving a heavy load (but suitable for driving tiny loads like LEDs). Whereas the MOSFET, in general, can be categorized as a small signal, medium power, or high power type. The last 2 types are meant to drive medium and heavy loads. Most MOSFETs are general purpose, but some are designed for RF.

Also the rated voltage for tri-state buffer is low (commonly <~5V, but CD4xxxx are <~20V) and the rated voltage for MOSFET can be up to 800V or higher.

Edited

Is an N-MOS FET an equivalent of a tri-state buffer, where the source is the input, the gate is the enable, and the drain is the output?

Technically, they are different as I have explained above. However, in the configuration you mentioned, it might appear to behave like a tri-state buffer. Unfortunately, it does not. Read on if you want to know why.

Before I go ahead to answer, here are some basic properties of NMOS. First, the VG of the NMOS needs to be appropriately biased to turn the NMOS on.

By default, both NMOS VGS thresholds are 1.5V in this simulator. On the left, the MOSFET is turned on with the Drain current of 4.8mA because its VGS > VGS(thres). On the right the current is nearly 0A because VGS < VGS(thres) (the non-zero current is due to a very tiny leakage current). Therefore: Property 1: To turn on the NMOS, VGS needs to be higher than VGS(thres), i.e., VG > VS + VGS(thres).

Second, the majority of the MOSFETs sold has its body (substrate) connected to the Source terminal, so you get a body diode that will conduct current from Source to Drain if the Source voltage is greater than the Drain voltage by more than the diode forward voltage. The following circuit demonstrates this.

The body diode of the NMOS is present, but it is not drawn in the Falstad simulator. Property 2: The drain current flows from Source to Drain when VS > VD + Vf, even the VG < VS + VGS(thres), where Vf is the diode forward voltage that is ~0.7V. Note that when VG < VS + VGS(thres), the MOSFET is off; the current flows through the diode and does not change for \$0V \le \textrm{VG} \le 6.5V\$.

Now, we are ready to address the question. The following are the results for circuit with the load connected to the output and GND. There are 4 different combinations of input + enable. The diode is explicitly added on the NMOS to show the intrinsic body diode.

Note that due to Property 1, the Enable terminal needs to be >6.5V (VGS(thres) = 1.5V) to allow VS to be driven high close to 5V when the Input terminal is 5V (see top left circuit). In my simulation, I set it to 10V to ensure that the NMOS is fully on. The four results show that it exhibits the tri-state properties in this configuration.

The following are the results for circuit with the load connected to the output and +5V.

When the Input terminal is 0V and the Enable terminal is 0V (disabled), we expect the LED to be off since the output should go Hi-Z. But the result shows that the LED is on (see bottom right circuit). It is on because of Property 2. This demonstrates that it fails to exhibit the tri-state properties in this configuration. We can fix this by using 2 NMOS back-to-back, but I digress.

So what do we learn from this?

1. The NMOS with its Drain as Input, Gate as Enable, and Source as Output fails to exhibit the tri-state properties. (So this answers your question.)
2. You need to feed the Enable terminal (Gate) with a higher voltage than the Input terminal in order to ensure the Output can be driven to the voltage level of the Input. This is a nuisance.
3. Tri-state buffer is a "buffer" gate, but yours is not a "buffer" gate. In fact, it behaves more like a "passthrough" gate. This means the input needs to be strong signal to drive the heavier output load because the input is directly driving the output load. For a buffer gate, the input can be a weak signal even you have a heavier load at the output.

Answer 2

In short: no.

A basic CMOS output has a PMOS device to pull the output up, and an NMOS device to pull it down.

A tri-state buffer has the means to turn both of those devices off. A simple inverter has one of them turned on - or another. The third state of a tri-state buffer is when neither output device is on. Since the output isn’t driven, it can assume any state imposed by external drive sources.

The fourth possible state is when both devices are on at the same time and there’s a shoot-through current from positive to negative supply. This dissipates quite a bit of power. In high-voltage or high-strentgh drivers this fourth state ends up in smoke after a short while. So it’s not desirable to say the least. But usually it is unavoidable and many CMOS digital circuits have a bit of shoot-through when they switch states.