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Reading questions like this one "How much does it cost to have a custom ASIC made?", I was wondering if there's some sort of equivalent to additive manufacturing that would lower the cost to getting prototype chips made. For example, can you "write" a chip with an electron beam or something? Carve it out with an AFM?

If not then why not, and who's working on this?

What if we restrict ourselves to analog chips / large geometries, are there any methods that then become feasible?

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  • \$\begingroup\$ Electron beam lithography and sharing wafers are useful in reducing mask costs for prototypes. Old technology masks (small wafers and coarse geometry) can be relatively affordable but a wafer fab is expensive to run. \$\endgroup\$ Commented Sep 27, 2016 at 20:31
  • \$\begingroup\$ Focused Ion Beam (FIB) is sometimes used to "patch" a prototype IC design, but it's very expensive and may not be able to reach all layers. A more practical approach would be something like a mask ROM, where the basic design is done in large volume, but stopping at the top layers. Then the contents of the ROM are configured with a custom top mask layer. It may be possible to do something similar with FPGA/CPLD, though for small scale it's still going to be hard to beat an FPGA. \$\endgroup\$
    – MarkU
    Commented Sep 27, 2016 at 20:31
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    \$\begingroup\$ There are structured ASICs, or pre-diffused wafers where only a few metal layers are customized. Gates are in the silicon and are custom-wired, like an FPGA but more efficient because configuration transistors are replaced by metal layers. \$\endgroup\$
    – Grabul
    Commented Sep 27, 2016 at 21:03
  • \$\begingroup\$ @TEMLIB: Can such technologies be used to handle low-power designs that would not be amenable to FPGAs? For example, if one wanted to prototype a simple sub-microamp RTC chip, an FPGA would be pretty useless but a device with a bunch of rows of N-channel and P-channel transistors, a separate N-well connection for each row of P-channel transistors, various lengths of vertical and horizontal runs, and one customizable via layer, would seem like it could be just the ticket. \$\endgroup\$
    – supercat
    Commented Oct 19, 2016 at 15:17

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Having a protoype ASIC manufactured is not very expensive when older technologies from 130nm up are used. The software tools needed are usually much more expensive since the market is quite small. From this point of view it does not make much sense to work on that problem.

It is possible to produce wafers and put them "on hold" at a certain stage during production. Doing this before the final layers of metal interconnect are made it is possible to continue production at a later point in time and produce a few variants of a chip. As a final resort focused ion beams can be used to remove and add tracks but this a very slow and expensive process.

A more interesting approach could be organic electronics where basically an ink-jet printer is used to generate electronic devices.

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An method often used is the multi project wafer: Using the wafer masks for different designs and sharing a wafer. Only a few dice are guaranteed to be manufactured. This is maybe the least expensive method to prototype designs.

But there is no additive feature, you have to be sure what you do when you tape out your design, even using a MPW. Hold Wafers in stop allows you to change minor things in your design, for example wiring.

See here the XFAB MPW time schedule.

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There's no such thing and there probably won't be anytime soon. Reasons include:

  1. N-wells and P-wells are are creating using dangerous (toxic/explosive) chemicals at high temperatures (often on the order of 1000C). Safety would obviously be a huge concern.

  2. IC feature sizes are ridiculously small, even on older processes. Additive manufacturing normally doesn't have very high precision.

  3. It's possible to edit ICs using a focused ion beam (FIB). You can both add and remove material. However, this process is expensive, failure-prone, and very-slow. Changing a few wires is a big deal. Connecting hundreds or thousands of transistors? Forget it.

  4. Unless you can do everything in one step in a single machine, you'd still need a clean room.

  5. Additive manufacturing doesn't solve the problems of design, testing, or quality control, all of which are nontrivial.

  6. Most importantly, there's already a cheap and effective alternative -- FPGAs.

Aside from being cool, it's not clear what problem additive manufacturing of ICs would solve. Who needs a tiny number of low-quality ASICs instead of a commercial ASIC, an FPGA, or an off-the-shelf chip available in quantity? If you just want to hook up a few dozen logic gates, you can do that on a circuit board.

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  • \$\begingroup\$ I guess the use case would be to prototype anything analog, since as you point out an FPGA is great for digital. Who needs a tiny number of low quality ASICs? Somebody trying to move up to producing a commercial ASIC. :) \$\endgroup\$
    – bcattle
    Commented Oct 19, 2016 at 22:36
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    \$\begingroup\$ I'm not sure the results would be good for analog. Would it even be possible to match transistors? And an IC prototype that uses a totally different manufacturing process from the final product would be useless. \$\endgroup\$
    – Adam Haun
    Commented Oct 20, 2016 at 0:22
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Yes, you can share space on a single die with others. A couple of fabs offer this. For example, MOSIS calls their program MPW, or Multi Project Wafers. The wiki link below has links to ~5 companies that offer it towards the bottom.

MOSIS MPW and the wiki.

Our VLSI class did this for a final class project in 0.5um MOSIS technology. Obviously a very, very old tech; but you can do this on newer techs as well. Plus for our needs 0.5um was good enough.

The price is proportional to the size you need (both area and I/O ports) and the technology node.

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