I am trying to get an optional dependency in GNU make. I tried to use $(wildcard) but am getting un-expected output:
test.mk:
a:
@echo "a"
b: $(wildcard a)
@echo "b"
@touch a
expected output:
$ make -f ./test.mk b
b
$ make -f ./test.mk b
a
b
actual output:
$ make -f ./test.mk b
b
$ make -f ./test.mk b
b
What am I missing about $(wildcard) ?
a
a file? Wildcard is used for patterns like*.c
right?