All Questions
6
questions
1
vote
2
answers
5k
views
VHDL serial adder test bench return UUUU
I've designed some week ago this serial adder, then i let it go for a while and now i would like to state if it works or not...
So the design is this one this one
And i report to you the testbench i'...
- 618
16
votes
8
answers
17k
views
What is the difference between testing and verification?
Every textbook I've seen makes a big deal of the fact that testing and verification are two different concepts. Yet none of them provides a clear (or clear enough to me, at last) distinction.
To ...
- 161
1
vote
2
answers
10k
views
No feasible entries for subprogram "CONV_INTEGER"
I have implemented a simple adder component with two inputs and one output.
...
- 111
1
vote
2
answers
2k
views
FPGA Simulation - VHDL Testbench
I've been designing a FPGA board that will become a single node of many in a computation cluster I am building for some scientific computing. The hope is to make it scale-able and allow me to update ...
- 113
4
votes
4
answers
8k
views
Test Cases for 16-bit Ripple Carry Adder
I'm working on a lab for a course I have on VHDL, and part of it is to implement an n-bit ripple carry adder and then test it as a 16 bit adder. My problem is that I don't really know HOW to test it, ...
- 91
19
votes
1
answer
670
views
Soft-CPU verification
I'm currently in the process of designing a simple CPU in VHDL using Xilinx ISE and ISIM. The design portion is going remarkably well, but I can't seem to figure out a way to do verification in a ...
- 3,775