All Questions
6
questions
2
votes
1
answer
45
views
Why I am having x as output from ReLU?
I am trying to test ReLU, but it always gives 'x' for the output.
...
-1
votes
2
answers
323
views
Test Verilog FSM for state with no reset
My professor gave us several Verilog test files to write Verilog test benches for. In the test bench, we're supposed to initialize the state to 0, apply random inputs, and check to see if we have ...
- 1
16
votes
8
answers
17k
views
What is the difference between testing and verification?
Every textbook I've seen makes a big deal of the fact that testing and verification are two different concepts. Yet none of them provides a clear (or clear enough to me, at last) distinction.
To ...
- 161
1
vote
2
answers
725
views
Difference between setting up clocks on Verilog
These two statements are used quite often, to set up clocks in test benches:
initial
begin
clock = 1'b0;
forever #5 clock = ~clock;
end
...
- 1,427
0
votes
1
answer
349
views
Verilog - Iterating Over All Cases In Testbench
In coursework, we are creating multiple circuits and explicitly testing every single case in Verilog. The way that we have been writing test benches so far is the following:
...
- 113
5
votes
5
answers
2k
views
Stress testing an FPGA's power supply
I have an FPGA (Xilinx Spartan 6) for which I want to stress test the power supply in "steps" (e.g. the FPGA runs in loops of 1 seconds: full steam for 900 ms, halted for 100 ms) to check that the ...
- 11.1k