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0 votes
2 answers
117 views

How do you justify energy band bending in an unbiased MOS Capacitor?

Here is a MOS Capacitor: (Image source: Chapter 5 of Modern Semiconductor Devices for Integrated Circuits by Dr. Chenming Hu) Now lets consider the idea that the gate voltage is held at 0V, just like ...
McSuperbX1's user avatar
0 votes
2 answers
208 views

Could we use holes in an NMOS?

In an NMOS we have a p-substrate, and we use a positive voltage to attract negative charge "to the top". But could we have used negative charge to attract holes instead and gotten a "...
user394334's user avatar
0 votes
1 answer
299 views

Is an NMOS device symmetrical with regard to its D and S pins? [duplicate]

Can D and S be swapped? (Assuming the body is not internally connected to S.) The structure of a MOSFET is totally symmetric. Even the LTspice simulation shows that it can be swapped. Does this ...
MichaelW's user avatar
  • 440
0 votes
2 answers
743 views

How does logic 1 get passed through an NMOS pass transistor?

I'm studying pass transistors. One thing I came across in several of the books is that when an NMOS has a logic state HIGH and the input terminal (the schematic below) is also HIGH, the output ...
Akib Ahmed Ishan's user avatar
0 votes
0 answers
67 views

How temperature difference does not affect transistors in CPUs?

Recently I learned about semi-conductors and some devices. Today I watched a video on youtube about a guy overclocking a cpu to 7.0 ghz, while cooling it with liquid nitrogen to -192 celsius degrees. ...
sliman jammal's user avatar
0 votes
2 answers
3k views

Deriving the NOT logic gate using PMOS logic

I recently started learning about Field Effect Transistors (FET's) and about the MOS circuit family. From my understanding NMOS is made from a p-type substrate and n-type source/drain, whereas the ...
Ski Mask's user avatar
  • 143
33 votes
3 answers
10k views

Why would a Intel 8080 chip be destroyed if +12 V is connected before −5 V?

The Intel 8080 is a classic microprocessor released in 1974, fabricated using an enhancement-mode NMOS process, and shows various unique characteristics related to this process, such as the ...
比尔盖子's user avatar
  • 7,218
0 votes
3 answers
663 views

Mosfet Threshold Voltage

from MOS theory we know that, in case of a P substrate, a Gate-Bulk voltage higher than a certain threshold value creates an inversion layer, in this case made of negative charges. This is also ...
Kinka-Byo's user avatar
  • 3,530
6 votes
1 answer
163 views

MOSFET switching on

I have a doubt. Consider an N-MOSFET: which is the voltage that can switch on it? The voltage between Gate and? Sometimes I read "between Gate and Bulk", sometimes "between Gate and Source", sometimes ...
Kinka-Byo's user avatar
  • 3,530
0 votes
1 answer
202 views

Identifying the logic function of this specific MOS layout

I am not sure about the functionality of the following MOS layout. I came up with the logic function AND(NOT(AB),C). Can anyone confirm or correct me ? PS: The steps I made are attached
Daher928's user avatar
1 vote
1 answer
1k views

MOSFET pinch-off [duplicate]

I have difficulties understanding what happens in MOS-FET-pinch-off: Take an N-MOSFET: Near the source the gate-bulk voltage is high enough to form an inversion layer. So we have electrons as ...
wolfgang6444's user avatar
-2 votes
1 answer
4k views

Channel doping change to control the threshold voltage in an NMOS

By increasing the P-doping in an NMOS, threshold voltage is increased. How does it happen? And why? And what elements do they use for this? can anyone give me a reference or explain?
Fateme's user avatar
  • 338
0 votes
1 answer
1k views

P substrate has electrons?

A P type semiconductor has only free holes and an N type has only free electrons. So in an NMOS, from where do the electrons in a lightly dope P substrate come to the gate and form an inversion layer?!...
Fateme's user avatar
  • 338
3 votes
1 answer
5k views

Why doesn't a capacitor connected to a MOSFET charge to VDD

If an nmos which has the gate and drain connected to VDD, and the source connected to a grounded capacitor, the nmos will start conducting and the capacitor will start charging as long as VDD > VTn (...
Blue7's user avatar
  • 1,655
14 votes
1 answer
8k views

Where are the depletion PMOS transistors?

In school, I was taught about PMOS and NMOS transistors, and about enhancement- and depletion-mode transistors. Here's the short version of what I understand: Enhancement means that the channel is ...
Stephen Collings's user avatar