All Questions
10
questions
1
vote
2
answers
112
views
Why simulation of single NMOS/PMOS on LTspice has big difference with manual calculation using Level 1 Standard Parameters?
I am researching the mode of operation on PMOS and NMOS using Level 1 standard parameters.
This is the information of the NMOS circuit to be designed.
Using transistor model level 1 parameters, ...
- 41
1
vote
1
answer
59
views
Will the saturation current through one of these NMOS circuits always be greater than the other?
Is there a definitive way to know for all cases if an NMOS would have a greater saturation current if a resistor R is connected to 1) the drain side or 2) the source side?
The assumption is that the ...
- 11
0
votes
2
answers
751
views
How does logic 1 get passed through an NMOS pass transistor?
I'm studying pass transistors. One thing I came across in several of the books is that when an NMOS has a logic state HIGH and the input terminal (the schematic below) is also HIGH, the output ...
0
votes
1
answer
359
views
What is the resulting Voltage Transfer characteristics of the modified CMOS-inverter circuit if NMOS and PMOS are interchanged?
What is the resulting Voltage Transfer characteristics of the modified CMOS-inverter circuit, if the positions of \$NMOS\$ and \$PMOS\$ are interchanged?
- 119
0
votes
2
answers
414
views
Find W/L and Vt of NMOS
I'm simply trying to find Vt and W/L for a given practice exam problem shown below:
The solution is given as:
Initially, I was trying to use the equation as shown in line 1 of the solution to ...
2
votes
1
answer
2k
views
Why is the gate drain capacitance in a mosfet zero when in saturation?
Suppose I have an NMOS. In the linear region the gate drain capacitance is modeled as \$C_{ox}\cdot w\cdot l(ov)\$ but it is modeled as zero when in the saturation region.
- 121
0
votes
3
answers
2k
views
Why the drop across NMOS enhancement mode load is V_t when driver is off?
In the enhancement load NMOS inverter, why is the voltage drop across the Transistor \$Q_1\$ when \$Q_2\$ is off, is \$V_t\$ ?
When \$V_{1}\$ is low, the transistor \$Q_1\$ is off. For the ...
- 133
1
vote
0
answers
105
views
Preference of MOS resistor as load in MOS inverter [closed]
Whys is a MOS resistor preferred over diffused resistor as load in design of a MOS inverter?
1
vote
3
answers
6k
views
Why does there have to be a load in MOS inverters?
I have been studying about inverters for a while. In the book that I was reading, inverters have been explained according to the type of load connected to the drain of the driving transistors ie. ...
- 1,177
0
votes
1
answer
95
views
After all the transients have settled down what would be the output voltage
Vo(0)=5 , what is Vo(infinity)
Can you please explain to me how i can get the answer.
- 11