All Questions
9
questions
1
vote
1
answer
161
views
CMOS (Energy Supply of voltage) [closed]
Can someone please explain why, when \$ln\$ is transitioning from low to high, the energy supplied is \$C_{vdd}\cdot V_{dd}^2\$?
0
votes
3
answers
573
views
Understanding the RDS(on) of an N-MOSFET
I need to calculate the time for C1 to discharge below 60 V using the following constant current sink if it is initially charged to 565 V (MOSFET's VGS(th): 4 V).
At first, I looked at the MOSFET as ...
- 41
0
votes
0
answers
167
views
Ultra-fast load switch
I have a question that I am assuming has a very easy answer (hopefully). I am trying to turn on and off the power to a pcb really fast, on the order of 1us. My problem is that my board has some bypass ...
- 15
0
votes
2
answers
64
views
Explanation of capacitor usage in this N-MOS application
I'd like to understand why capacitor is used in this circuit instead of connecting PWM pin directly to N-MOS.
How does Q3 have HIGH reference with no direct connection?
What kind of advantage I have ...
- 457
0
votes
0
answers
527
views
What does a capacitor in parallel with a pull up resistor at the drain of a N mosfet do?
I am analyzing a past design that uses a GPIO to toggle the N mosfet on and off. The resistor is just a super long winded trace on a separate board. There is a capacitor in parallel with the resistor. ...
- 39
0
votes
0
answers
104
views
2 N-MOSFETs in series
I'm trying to design a circuit to charge a capacitor bank with constant (limited) current and then discharge the capacitors through an LED. I've come up with the circuit in the schematic below, ...
- 868
0
votes
1
answer
2k
views
Working of NMOS as a capacitor
I came across instances where NMOS was used as a capacitor in analog circuits. This is done by shorting the drain and source. The drain/source acts as one terminal of the capacitor while gate acts as ...
1
vote
1
answer
90
views
Voltage on Source Node
I am trying to analyze this circuit, the cap is initially charged to 3 V, the supply is 3 V. The NMOS threshold voltage is 0.7. Next the voltage at gate steps from 0V to 3V, what would be the voltage ...
- 421
2
votes
1
answer
2k
views
Why is the gate drain capacitance in a mosfet zero when in saturation?
Suppose I have an NMOS. In the linear region the gate drain capacitance is modeled as \$C_{ox}\cdot w\cdot l(ov)\$ but it is modeled as zero when in the saturation region.
- 121