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Questions tagged [architecture]

As used in EE.SE, it describes the physical topology and techniques of routing power, ground, data and control lines across a given area. This could be a CPU/MPU, circuit board or the lighting of LED's around a pool. Electrical parameters and physical (object) constraints ultimately decide the most efficient and safe layout. The term 'architecture' has no scale (size) until it is defined by schematics, diagrams, blue prints.

2 votes
0 answers
35 views

Soft power-off compatible with two different hardware architectures

I've been tasked with designing a single PCB that will (amongst other) provide soft-power off feature to two different products with different hardware architectures. The notable differences between ...
Lars Petersson's user avatar
1 vote
0 answers
144 views

How to get USB 3.x power but with data limited to USB 2.0 HS?

I am designing a device with a few interesting requirements. Due to power requirements, we need to draw 900mA, but due to isolation requirements, we're limited to the 480Mbps rate for our primary ...
mbengineer's user avatar
0 votes
1 answer
201 views

Is there a specific meaning for these arrows in the architecture of a microcontroller?

Yellow mark Green mark Blue mark Do these arrow signs mean something specific? Also, if there are other types, where can I go to read about them? Source : here Edited :
Just doin Gods work's user avatar
2 votes
1 answer
984 views

How do you fit so many instructions on a 8-bit processor?

I will preface this that it is highly likely that I have misunderstood how Harvard architecture works, but I cannot understand how an 8-bit instruction set, say the ATmega128 for example, can contain ...
Lyndon Alcock's user avatar
2 votes
1 answer
392 views

ADS8598S - how to connect to a MCU - general Architecture question

For a future project I'd like to use the ADS8598S from Texas Instruments, which is a "higher speed" 8 Channel simultanously sampling ADC with 18 Bits and a max. Sample rate of 200 kSPS per ...
pm4812's user avatar
  • 67
10 votes
7 answers
5k views

How do 16-bit addresses work inside 8-bit data bus processors?

As a project I am building a small 8-bit RISC processor out of discrete ICs. I have 17 instructions and cannot fit all information into instructions that are only one byte, so I have been thinking ...
David777's user avatar
  • 1,555
11 votes
3 answers
3k views

Why do we see one, unified memory address space in ARM Cortex-M core based MCUs even though they have Harvard architecture?

Most of the ARM Cortex-M core based MCUs have Harvard architecture (except for Cortex-M0 and M0+.) The thing I do not understand is that why we see only one memory address space. For example, in tge ...
gvg's user avatar
  • 163
1 vote
0 answers
40 views

Are coarse-grained reconfigurable architectures a subset of dataflow architecture?

By definition, dataflow architectures consist of large modules in the dataflow path, such as adders and multipliers for integer, floating-point, or fixed-point computation. Hence, are coarse-grained ...
Giovanni's user avatar
0 votes
1 answer
106 views

Power outage detection to kickstart a safe shutdown and data retention process

I plan a system that operates on a 5v rail. The power is supplied from an outside DC source. The 5 V powers an RPI CM4 and other components that are controlled by it. The whole system requires up to 5 ...
metsik's user avatar
  • 173
3 votes
2 answers
178 views

Soft errors from SEUs/SETs in early 8-bit microprocessors?

Why is it that soft errors due to single-event upsets/transients never seemed to be a problem in early 8-bit microprocessors, like the MOS 6502 or the Zilog Z80? The microprocessors themselves were ...
H2SO4's user avatar
  • 131
0 votes
1 answer
83 views

Help needed in selecting the power architecture for my project [closed]

I had some trouble in finalizing the power architecture for my upcoming project. In a brief summary about the project, I am using a GPS device to acquire location of the vehicle and control two ...
Rohit_Kashyap's user avatar
0 votes
2 answers
219 views

What are common ways that modern processors handle data hazards with asynchronous registers

I'm trying to design a processor in VHDL. While the base instruction set is done, I'm having trouble building on top of it. Specifically, I'm implementing control and status registers (CSRs), which ...
tuskiomi's user avatar
  • 687
1 vote
1 answer
57 views

Software for system architecture capture

I work as an electronics engineer and I'm starting to create a new device. This device will be significantly more complex than any project i've undertaken so far and will require close interaction ...
benp's user avatar
  • 11
4 votes
2 answers
12k views

Electronic Controller Unit (ECU) Vs. MCU

Isn't the Electronic Controller Unit (which are used in automotive applications) a Microcontroller it self? What is the difference between them in architectural point of view?
Lavender's user avatar
  • 527
0 votes
1 answer
189 views

IA 32 architecture segmentation

I was reading the 10th edition of "Operating System Concepts" written by Abraham Silberschatz and many others. It says about IA-32 architecture's segmentation: The IA-32 architecture allows a ...
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