Datasheet: https://www.ti.com/lit/ds/symlink/tps62136.pdf?ts=1719417594079
The pad pitch is 0.5mm (p.42):
IPC-7351 describes solder joint geometry and terms. This is identified as a flat no-lead solder joint. LGA or CSP style pads are similar, depending on whether the side flanks are wettable (and thus show a toe fillet), and the pad arrangement.
Heel is irrelevant here, as the bars cross the package. There are two toe fillets, and two side fillets. Table 3-13 (IPC-7351 Feb. 2005) suggests -0.04mm side and 0.2-0.4mm toe fillet (depending on component density class*).
Given the lands are 0.2mm minimum width plus 0.1mm maximum tolerance, I would be perfectly comfortable using 0.2 + 0.1 - 0.04 = 0.26mm wide pads on the PCB. This should be easy to fab most anywhere. They can be shaved down to 0.23mm or so to reserve a little more space for soldermask, but less than 0.2 I might be concerned with strength and alignment.
*And, more informally, how well you want to be able to hand-touch-up the solder joints using a soldering iron. This isn't elaborated on by IPC here, but from my own experience, fillets of 0.3mm are difficult to reach, short of a pointy (SMT rework) tip. You may therefore prefer larger toe dimensions for iron-assisted rework. Of course being a no-lead part, there isn't a whole lot of value an iron can provide, so this is of low importance here.
On the following page, TI suggests a SMD (soldermask defined) footprint, which not only requires tighter copper tolerances (oversized pads = closer proximity), but tighter soldermask tolerances as well -- usually this is advertised as LDI (laser direct imaged) as opposed to traditional photoimaged (or even inkjet or silkscreened) mask. A mix of SMD and NSMD (as they seem to suggest) sounds like a poor idea to me; there will be a systematic error between both imaging steps, and there doesn't seem to be any reason not to follow the same practice on all pads (they're all the same pitch and width range, and there's ample space between bar sides and pin heels).
For prototype, I would personally recommend a NSMD footprint, with 0.26mm (Cu) pads, and soldermask expansion by rule (typically ~0.07mm; the exact value hardly matters as proto fabs generally adjust it to suit their process anyway). This leaves 0.24mm space between pads, which should be producible by most anyone; the remaining soldermask web between pads may be too small to produce (<0.1mm?), and should be removed automatically in that case (or you can remove it yourself). Or as mentioned, somewhat thinner pads are also acceptable.
Relying on library footprints without verification against industry practices (such as IPC) or datasheet recommendations, tends to be a good way to learn lessons -- libraries are poorly vetted, may not have been produced at all (let alone in good yield), symbols range from standard to ugly and in all range of scaling; in all, you end up with inconsistent designs on both the SCH and PCB. There is much to learn, of course, both in working with EDA software itself, and in developing ones' own style and preferences, as well as where the solder hits the road, so to speak.
The best advice I can give, is always be playing around: try different symbols, schematic styles, figure out what's readable and what's not, work to that; check library pinouts and namings against datasheets, learn to read package drawings (drafting in general, and GD&T (Geometric Dimensioning and Tolerancing)), read up on IPC standards and how they're used, check footprints against drawings and calculations, make sure everything should fit; and draw whatever silkscreen and mechanical layers you find suitable for your process.
A closing note: in a professional context, the footprint dimensions should be ultimately up to the assembly team putting the board together. IPC recommendations are best used as a starting point: the least-bad way to solder any part, in any given style, by any CM (contract manufacturer). Actual dimensions may vary with the part (depending on how they tolerance it, and what the tolerances of real parts are), plating/lead finish, and even the solder formulation (alloy and flux) and how it's applied (stencil and thickness).
