Lots of electrical noise at boost converter output

Question

I'm trying to implement a boost converter using TI's TPS55340.

After spinning up the design, I have found that the output ripple is almost 8x what I expected to see given my design parameters. First, let's get into the design, schematic and layout.

In short, my design parameters:

• Input voltage: 11-13 V
• Output Voltage: 16 V @ ~3 A (WEBENCH set to 2.91 A)

Plugging this into WEBENCH resulted in the following implementation (link to HTML):

I translated this into KiCAD as follows:

And here's the region of my PCB where the boost converter is realized:

The input 12 V is input to the board less than 3 cm away via a DC barrel jack.

There is a mistake in the layout, I should not have sliced through the 16 V output plane with the V_SW test point, but I have fixed this with a few bodge wires. Here is a photo of the assembled region of the circuit:

You'll likely be interested in the critical components to implement the boost converter:

• L1 is SRN6045TA-3R3Y
• D1 is SK320A
• C10 is C1206C222K5GEC7210
• C11 is UUD1E560MCL1GS

Using my benchtop power supply set to 12 V, and my DC load configured to draw 0.1 A, 0.5 A and 1 A, I measured the output using my oscilloscope and took screenshots. In each figure the 12 V input is the blue trace and the output is the yellow. Both channels are in AC coupling mode, and neither probe is using the ground alligator clip -- both are using the ring-tip ground spring.

0.1 A:

0.5 A:

1 A:

The Vpp of the output being all the way up near 3 V is way out of spec for the design, according to the WEBENCH model it should be less than 57.5 mV.

I think the problem stems from a weak output diode. I notice that the part gets pretty hot during operation. What do you think?

If there is anything missing you'd like to see from the design, let me know.

Edit #1! Feedback has been incorporated, original design bodged:

The replacement parts have arrived and I've installed them on the PCB.

C11 is again 56uF but now has a much lower ESR. It's PN is 25SVPF56M.

C10 is now 1uF (up from 2.2nF). It's PN is
C1206C105K3RAC7800.

Here are the results. Same setup as last time, input power set to 12V, DC electronic load providing the load. This time we're only probing the output of the circuit.

0.1A:

0.5A:

1A:

Here is the modified board (& probing setup):

The results here are mixed. At low current, the results are greatly improved. However, up at 1A there is still 2V of ripple on the output vs. the expected value of ~50mV.

This is likely due to the incorrect layout as pointed out by commenters.

Before I re-design the board to fix the errors, do these results point to additional problems with the design?

Edit #2! Design review of second revision:

Per the feedback from Jonathan S. and bobflux, I've come up with a second revision of this board and hope to submit it for more feedback prior to getting it manufactured.

In summary, the changes are as follows:

• Removed large test points that sliced up the output pour.
• Added a larger output diode that can handle more current.
• Added a copper pour below the output diode to remove heat.
• Generally tightened output layout.
• Add larger ground plane below the boost converter.
• C10 is now 1uF.
• C11 is a much lower ESR 56uF cap, 25SVPF56M.

Here's the schematic:

Here's the complete layout, followed by the front and back copper layers:

I'll ask below for feedback, integrate it and then keep posting along with my progress.

Answer 1

The diode is innocent. What you're seeing there is the effect of the output bulk capacitor's ESR (C11). According to the Digi-Key page you linked, its ESR is 0.44 Ohms. Given the waveform of the 1A trace, we can conclude that the converter is operating just at the edge of discontinuous conduction mode. The inductor ripple current should be about 2x the output current, which is 2A peak-to-peak in this operating mode. Multiplied with the output cap's ESR, you get an output ripple of about 1Vpp. This matches the triangular ripple waveform on the 1A oscilloscope trace.

The output bulk capacitor should ideally have 20mOhms ESR or less. Yours has almost 25x of that.

You simply chose the wrong capacitor. C11 needs to be an Al-poly type. The Panasonic 25SVPF56M would fit the existing footprint. If you want some more capacitance, the Nichicon RSA1E101MCN1GS might also be a good choice.

The very short, large voltage transients that are superimposed on the triangular ripple waveform point at a lack of high-frequency bypassing, which means that C10 is also wrong. It should have much larger capacitance, i.e. 1µF X7R.

Answer 2

It's the output cap. According the the datasheet, C11 has maximum ripple current of 230mA RMS and 0.44 ohms impedance at 100kHz, some of this impedance is capacitive but the rest is 30-40 mOhms ESR.

It should also have an inductance around 4nH due to its construction.

You would need a cap rated for the ripple current and with low ESR/inductance.

The Vpp of the output being all the way up near 3 V is way out of spec for the design

If your DC-DC chip switches 1A in 10ns, with an output cap having 4nH of inductance, that results in e=Ldi/dt=0.4V spikes. In your case the spikes are much higher, because the cut in the output copper pour increases the effective inductance of your cap.

The rest of the ripple is due to output cap ESR.

The output cap receives a much higher ripple current that it is rated for so it will heat up and this will shorten its life.

A quick fix would be to solder the highest value X7R cap that will fit on C10's footprint, unfortunately C10 has no close vias to the ground plane which increases its inductance.

• All the test points have to go. If you need them, put them on the back or anywhere else, but do not cut the copper pours: you need them to be whole for low inductance.

• If possible, use all ceramic output caps. The usual 10µF MLCC has about 3 mOhms ESR, 1-2nH ESL depending on layout, and due to the extremely low ESR it can take a huge ripple current, ridiculous for its size. Using several in parallel means even lower ESR and ESL. In these low values the only electrolytic caps that could compete would be polymers, but... ceramics will simply be cheaper and have much lower inductance too.

In fact you can probably use the same MLCCs on the input and output, to get quantity discount.

If the chip does not like all-ceramic output caps, pick a chip that does.

There is always some trace impedance in series with your caps. It's better if the output node is taken on the proper side of this impedance. That's why I added a cut (in green) in the output pour.

Regarding capacitor choice, 56µF 25V is an annoying value. The reason is a 10µF X7R 1206 MLCC only has a remaining capacitance of 3µF at 16V (see here, I used GRM31CR71E106MA12K). So if you use MLCCs only you need many, which takes up space. On the plus side, you get excellent ESR and ESL. So 56µF is too high for ceramics... but on the other hand, if you want to use an electrolytic cap, 56µF is too low because you'd get more low-ESR options with a higher value.

Note in the Webench simulation you linked, you can click on the parts and it will give you exact part numbers, which it also uses in the simulation. It recommends an OSCON polymer cap (same as Jonathan S quotes in his answer). Webench also takes into account inductor ESR.

I think the problem stems from a weak output diode. I notice that the part gets pretty hot during operation. What do you think?

Webench gives 2.76W diode loss, which is OK for the diode it recommends (it's a DPAK) but the much smaller diode you used will most likely overheat, the package is too small to conduct this amount of power into the PCB copper, and there is not enough copper to cool it. Also it's a lower current diode, so while it will have lower capacitance, thus lower switching losses in the MOSFET, its Vf at 3A is higher than the recommended diode, which increases conduction losses.

I see you made a very small PCB, so if you need it to be this tiny I would recommend a synchronous boost converter for the single reason of getting rid of the diode, and thus its dissipation, and thus the area required to cool it.

---

For the new version:

Answer 3

If you look carefully at the Webench schematic, you'll see that you've ignored the specifications that were purposefully red-colored as being important :)

You also should show a photo of how exactly you probe your prototype. I bet you a bit of what we see is the resonance of the improper probing setup. You need to use very short, concentric probing tip that connects both the tip and the ground ring of the probe to the test points with <1cm of distance between the test point ground and probe tip ground ring. For this, the probe tip "grabber" must be removed, and ground clip cannot be used!

In the revised layout, you'll do well to provide test points specifically designed to accept the pin spacing of the high-frequency probing attachment on the scope probe. These accessories are typically provided with the probe.

I also don't see a continuous ground plane under the switcher.