I am hoping for some feedback, thoughts, or clarity regarding a discrepancy in output capacitor values between what I calculate, a reference design in the datasheet for TI's controller, and TI's WEBENCH reference design. I'm using the TI TPS40210 boost controller. The board takes a 14v-28v signal and boosts it to 48Vdc out at 2A with a desired ripple voltage of 100mV. The duty cycle is 71.2% max and has a switching frequency of 430KHz.
Using the following equation for Cout:
Cout = Iout(Duty Cycle/Vripple)(1/Switch Frequency)
I calculate a value of 33uF
reviewing TI's datasheet, and following a reference design they have for a 12V to 24V boost regulator, they provide the following equation to calculate Cout:
Cout = 8(Iout x D/Vripple)(1/Fsw)
using my design criteria and this equation, I calculate Cout to be 265uF
adding to my confusion, I used TI's WEBENCH for the first time. The reference design it produced suggests an output capacitance of
56uF (qt 2) with an additional ceramic capacitance of 2.2uF.
given that none of these values agree, I'm hoping for a sanity check/clarity on a few points
My main questions are:
does anyone know where/what that constant 8 value is for in TI's reference design?
In the WEBENCH reference design, (This is my first time using it) does the 56uF (qt 2) mean 2 parallel Capacitors of 56uF for a total of 112uF?
While the 33uF output I calculated is a minimum, will WEBENCH size up the capacitors to give better Ripple/Transient performance automatically?
Does anyone know what/how the WEBENCH designs factor in, inrush currents when sizing output capacitance?
Because of wide gaps in all three Cout values, I'm second guessing a lot.
I've included photos for the TI datasheet equation and the WEBENCH design for reference.
Thanks for your help!