Output capacitance deviation for TI's TPS40210 Boost Converter application

Question

I am hoping for some feedback, thoughts, or clarity regarding a discrepancy in output capacitor values between what I calculate, a reference design in the datasheet for TI's controller, and TI's WEBENCH reference design. I'm using the TI TPS40210 boost controller. The board takes a 14v-28v signal and boosts it to 48Vdc out at 2A with a desired ripple voltage of 100mV. The duty cycle is 71.2% max and has a switching frequency of 430KHz.

Using the following equation for Cout:

Cout = Iout(Duty Cycle/Vripple)(1/Switch Frequency)

I calculate a value of 33uF

reviewing TI's datasheet, and following a reference design they have for a 12V to 24V boost regulator, they provide the following equation to calculate Cout:

Cout = 8(Iout x D/Vripple)(1/Fsw)

using my design criteria and this equation, I calculate Cout to be 265uF

adding to my confusion, I used TI's WEBENCH for the first time. The reference design it produced suggests an output capacitance of

56uF (qt 2) with an additional ceramic capacitance of 2.2uF.

given that none of these values agree, I'm hoping for a sanity check/clarity on a few points

My main questions are:

1. does anyone know where/what that constant 8 value is for in TI's reference design?

2. In the WEBENCH reference design, (This is my first time using it) does the 56uF (qt 2) mean 2 parallel Capacitors of 56uF for a total of 112uF?

3. While the 33uF output I calculated is a minimum, will WEBENCH size up the capacitors to give better Ripple/Transient performance automatically?

4. Does anyone know what/how the WEBENCH designs factor in, inrush currents when sizing output capacitance?

Because of wide gaps in all three Cout values, I'm second guessing a lot.

I've included photos for the TI datasheet equation and the WEBENCH design for reference.

Thanks for your help!

Answer 1

does anyone know where/what that constant 8 value is for in TI's reference design?

For all the formulas you refer to, different assumptions (zero ESR, CCM operation across the whole range, etc) have been made. So, you can take none of them as an absolute reference (The first formula, as you already know, gives you a theoretical "minimum" based on some assumptions, for example).

Normally, when you select the boost choke, you should select a \$\Delta I_L\$ (ripple current for the choke) first. This ripple current will flow through the output capacitor (and the DC component will pass to the load) so the output voltage will change by some amount (ripple). From \$i_c = C \ dv_c/dt\$ (or \$i = dq/dt\$ from the conservation of charge) you can calculate a ripple or a capacitance from expected ripple. But this doesn't take the ESR and the ripple it brings into account.

In the WEBENCH reference design, (This is my first time using it) does the 56uF (qt 2) mean 2 parallel Capacitors of 56uF for a total of 112uF?

It's Qty. = 2, as clearly seen from the schematic. Qty is the short form of quantity. So yes, 2 of 56 uF electrolytics will be connected in parallel, and another 2.2 uF ceramic for high frequency components of the ripple.

While the 33uF output I calculated is a minimum, will WEBENCH size up the capacitors to give better Ripple/Transient performance automatically?

Does anyone know what/how the WEBENCH designs factor in, inrush currents when sizing output capacitance?

The tool is optimised for different things such as cost/performance ratio, dynamic behaviour, physical size, operating conditions, life etc. Especially life is a serious limiting factor here because the biggest impact comes from the electrolytics i.e. as they get hotter their lifespan decreases.

As I stated above, to calculate the boost inductance, an assumption for the inductor ripple current needs to be made. This ripple current will flow through the output capacitor but it might be too high so the capacitors may get hotter. To overcome this problem the ripple needs to be reduced. But a smaller ripple brings larger inductance. Larger inductance means larger size (larger core size and/or more turns). Larger inductance with thinner wires brings smaller size but higher loss (due to the high DCR); larger inductance with thicker wires brings lower loss but larger size.

So the tool tries to find the optimum between cost, life, size, operating conditions, and maybe other things. So it's quite normal for the tool to end up with multiple electrolytics or different values.

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The formulas and the design tools give you the starting point. But when you have the physical circuit at hand, the operating parameters may differ by some amount. So the best thing to do is to finalise the circuit on the bench by taking measurements for different conditions and finding the best values that suit your needs.