PWR and GND plane make a capacitor with the dielectic in between them. The closer the two planes are physically, the higher the electrical coupling and thus the capacitance between them.
Power delivery network relies a lot on decoupling capacitors to smooth out noise on the power supply rails. Does the power plane capacitance have any benefit in this regard?
Yes. With typical capacitance of low ~nF and essentially no stray inductance, it may serve as filtering at very high frequencies, and acts as a nearly ideal connection between all points on the board.
The fairly low capacitance can create issues at the highest frequencies (10-100MHz) [1], for which it's important to keep track of what (small) bypasses are attached to the plane -- you want to avoid it resonating against the bypasses' inductance, but rather be damped by their ESR.
That is, for the total parallel equivalent of all bypasses, you want \$ESR > \sqrt{\frac{ESL}{C}}\$, for various combinations of C's and their ESLs. So, between groups of bypasses, between plane and bypasses, etc.
You might not be able to make such a parallel equivalent, but take this as an example for sake of discussion, supposing it is reasonable. It is actually exact when every bypass is of the same value and type, and component body size and connection (traces and vias) geometry (i.e., they have the same ESL): then they will have the same resonant frequency, and act in parallel.
It's not generally feasible to apply damping resistance (such as from bulk capacitance i.e. relatively large capacitors with modest internal ESR, or ceramics with explicit series resistance) to the plane, because the required inductance is so minuscule; rather, the effect will be using all the small bypasses dotted around, acting in parallel, thus reducing their collective (parallel equivalent) ESL low enough to be useful in this way.
Put even more simply: you can't simply put an R+C snubber across it, because the impedance is so low, you can't possible make a single element with low enough inductance to do the job. Rather it will end up as many elements in parallel, distributed.
Regarding the resonances:
In practice, bypasses in different locations will have slightly different inductance to, and through, the plane, because it is not actually ideal; and therefore they will have slightly different resonant frequencies, and there will be various resonant modes mixed between them. In that case, the PDN impedance spectrum (say, as measured at any given pair of VCC/GND pins) may have a multitude of peaks (as many as there are bypass capacitors); but the maximum value across all peaks will still be limited by using the same constraint as above. (That is: there are more combinations of ESL and C we might have to check to be sure. Especially if values differ across the board, e.g. some large (couple uF) ceramics sit in one corner, opposite a bunch of tiny ones elsewhere.)
[1] Note that frequencies above 100MHz or so are generally not effective to handle on board; hence FPGAs, CPUs, SoCs, etc. typically have local bypass capacitors attached via interposer or stacked-die connections. The key is that these components demand quite a low impedance (e.g. some amperes of current draw at 1V), so despite using many power and ground pins in parallel, their supply bandwidth is still limited by lead inductance.
Indeed, ICs are even limited by the inductance of connections to their chip-attached bypass, too; high-speed chip design can be optimized to such a level that, relative to a given clock edge, the remaining (inactive during the same edge) logic circuitry itself -- sheer transistor capacitances alone -- acts as on-die bypass, as well as the interleaved metal layers distributing supply across the chip, and so on.
At higher impedances, say for RF amplifiers, on-board bypass remains useful to much higher frequencies. This is why we don't care that a 0.1uF capacitor is inductive at 1GHz, it's still an effective RF short circuit compared to the say 50Ω system impedance, and therefore is a useful bypass as such. (We might require additional filtering to contain the residual RF dropped across its ESL, though.)
