Power distribution on a board with large number of voltage rails

Question

Complex FPGA boards nowadays can have a large number of voltage rails like 5V, 3.3V, 2.5V, 1.8V, 1.2V and seprate analogue and digital supplies and then separate voltage rails for specific components like DDR memories.

From what I know, we need to use power planes in this case to distribute the power. In this case, the square/rectangle shape of a copper plane will be split into sections akin to floorplan of a house where different regions will be dedicated to different voltage rails.

The confusion I have is, how does it all connect together. The voltage regulators will be in a specific region/section of the board. From there we need to connect them to power planes on the other side of the board. We need to decide how many power planes we need as well and the voltage regulators will have to connect to planes on different layers. And we need to make sure that the noise on the rails is not so much that the component fails.

How is the "floorplan" and quantity of power planes decided? Do we need to distribute the voltage regulators everywhere on the board like SMPS on one side (or on bottom) and then lot of linear regulators connected to tiny power planes in middle of the PCB. Or all SMPS and linear regulators on one side of the board and then connected to planes everywhere somehow.

I am an electronic engineer so you do not need to write too much. If you could guide me to some application note, that would be great. All the search I have done on google so far, just leads me to topic of ground planes and whether they should be split for analogue-digital grounds or not. I am not looking for that.

Answer 1

You can get by without planes, unless you have specific stringent requirements for low power supply impedance above ~100 MHz.

FPGA chips (like other ASICs) do include on-chip and/or on-carrier decoupling capacitors. So the mere fact that the chip works at high frequencies is not enough to tell whether you have such requirements. Check the datasheet, it should specify the maximum power supply impedance over frequency.

If such requirements do not exist, it is good enough to place a voltage regulator in the general vicinity of the FPGA, route power to the regulator, and use a short patch to connect the regulator output, the FPGA pins and a bank of decoupling capacitors for low impedance between approx. 10 kHz - 100 MHz.

Further reading: Altera/Intel guide about the influence of various decoupling schemes on power supply impedance over frequency