Questions tagged [power-integrity]
The power-integrity tag has no usage guidance.
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Sony IMX421 Eval board with IMX422 Sensor - produces odd repeating patterns instead of true images
I am working on an application that involves use of a Sony IMX422 CMOS image sensor - namely writing VHDL code to act as a receiver interface to the sensor over an SLVS bus. the setup involves a ...
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How do you de-embed a shorted 2-port fixture?
I've been working through reproducing Steve Sandler's 2-port shunt-through measurements (2019 SIJ article, Picotest slide-deck). My target is to measure capacitors with ESR down to 1 mΩ with an ...
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Power integrity design review of LED driver and audio amplifier PCB
I am seeking advice on improving the power integrity of a PCB featuring a HT16K33 driving 6 segment LEDs and a YX8002 (equivalent to LM4871) audio amplifier. Decoupling capacitors C7 and C16 are ...
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Is it possible to know through simulation whether we have the right number of decoupling capacitors?
More decoupling capacitors than a certain amount does not improve the power integrity much. I am not sure if this is a case of diminishing returns or a case of reaching a wall.
How exactly can we ...
- 12k
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Connecting '-' terminal of the power supply to the earth GND
I've already asked a similar question in the past, but I want to make sure I understood things correctly.
Attached is the current lab setup for my chip testing. The green square represents the main ...
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Track vs Via impact on power integrity
This question is from perspective of power integrity and not signal integrity. Power can be delivered from VRM to an IC using copper tracks and vias. Both of these have inductance and we want to ...
- 12k
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FPGA decoupling capacitors
FPGAs have among the largest packages and the most voltage rails. This is especially true of the high end devices e.g Stratix, Virtex Ultrascale+ e.t.c. This means a whole lot of decoupling capacitors....
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Shall I connect '-' terminal of power supply to earth GND (green terminal)?
Attached is the current lab setup for my chip testing. The green square represents the main PCB board, and little blue square represents the chip. The chip needs separate VDD voltage for its analog ...
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Using main board power supply rails in add-on boards
Many boards come with board-board connectors that can be used to connect another PCB to add new functionality. There are many examples of this. Some that come to mind are Arduino shield, Click boards™,...
- 12k
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Is there any benefit of the power plane capacitance to PDN?
PWR and GND plane make a capacitor with the dielectic in between them. The closer the two planes are physically, the higher the electrical coupling and thus the capacitance between them.
Power ...
- 12k
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Bulk capacitance near a processor affecting converter transient response
Here is my question: why do manufacturers of processors and FPGAs prescribe adding hundreds or thousands of microfarads of bulk capacitance next to their part?
The IGLOO2, for example, recommends a ...
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How to calculate target impedance for the power trace if it is connected to multiple loads?
In this image, the source 3.3V, which is going to three loads(U1,U2,U3), that consumes current of 2A,0.5A and 1A respectively,
As the total current is 3.5A.
Lets consider allowable ripple,
U1-2%
U2-3%
...
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S parameter model of the capacitor
For same capacitor, there is no s-parameter model, so can we use the model from other manufacturer of the same spec.
Eg:
Caps with model - C0603C104K5RACTU - KEMET - Cap, Cer-X7R, 0.1uF, 50V, 10%, ...
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How does current flow in multiple vias?
How does current travel in multiple vias from one layer to other?
For example, we connect four vias, each of which has a limit of 1.3A each from power plane to sink device. If the sink draws 4A of ...
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I2C bus pollutes power rail
Working on a new revision of a design with a new I2C LED driver connected to
SAM S70 Cortex-M7, I noticed some high speed ripple on 5V rail when using a 1Ghz scope.
The PCB has 2 I2C buses and both ...
