How to sample the read data from blocking logic safely by using the interface of SystemVerilog?

Question

I'm trying to read data from combinational logic.

module my_reg(;
  ...
  output reg [31:0] rdata;
)
  ....
  always @(data)
  rdata = 32'h18;

and this dut's value is interfaced with a testbench.

module test;
...
my_interfcae _if();

my_dut u_my_dut (
...
.HRDATA    (_if.HRDATA),
...
)

and the interface is implemented as below:

interface my_interface;
...
logic [31:0] HRDATA;
...
endinterface

The problem is that I get the HRDATA at the first 'x in the UVM Driver.

In UVM_DRIVER:

 ...
 req.HRDATA = ahb_if.HRDATA;
 $display("R3RDATA: %0h", ahb_if.HRDATA);
 ...

Especially, the waveform I captured, you can see the HRDATA has 'h00000012 ,'h00000034 and 'h00000056 so on.

This is the print out from $display("R3RDATA: %0h", ahb_if.HRDATA); in Driver.

How to sample the read data from blocking logic safely in the interface of SystemVerilog without F/F at that point?

Answer 1

You have a simulation race condition. You are trying to display a signal value at the same time it is changing. One way to fix it is to add delay before you display. For example, change:

$display("R3RDATA: %0h", ahb_if.HRDATA);

to:

#1 $display("R3RDATA: %0h", ahb_if.HRDATA);

Another way is to change $display to $strobe.

---

You should always display the simulation time when debugging, something like this:

$display($time, " R3RDATA: %0h", ahb_if.HRDATA);

Since you are using UVM, you should always use `uvm_info instead of $display since it displays the time by default:

#1 `uvm_info ...