Are SR latches bad in ASIC design?

Question

I am implementing an ASIC design, and my current solution for a problem requires an SR latch. I've always been told that latches are bad in FPGA and ASIC designs, but never got a proper answer as to why. After doing some research, I found out that most modern FPGAs have the ability to use some of their registers as latches (like in the Spartan-6 serie), and that most ASIC cell libraries have latches cells.

I'm guessing that involontarily inferred latches are bad, but intended ones aren't if used properly. They can reduce testability in ASICs and could cause problems in timing analysis, but aren't fundamentally bad.

But I've read somewhere (Intel's website if I recall correctly, but I can't find it again) that SR latches can cause glitches and stability issues. There was something about NOR/NAND loops which create problems. No further information where provided so I don't understand why this would be the case. Are SR latches really a bad idea in an asynchronous ASIC design? Or is this just a general "don't use latches" recommendation?

In my design, instead of using two NOR I manually instantiated a D latch with set and reset, and grounded D and EN.

Answer 1

An SR latch has a transition that is problematic. In a NOR implemented SR latch, a nearly simultaneous transition of both inputs high to both inputs low can cause the latch to enter a metastable state or oscillate. Depending upon your circuit, such behavior may cause serious problems, even if it only occurs once in a 1000, or once in a million transitions. A NAND implemented SR latch has a similar problem when both inputs transition nearly simultaneously from low to high.

This issue with SR latches does not occur if either a) you avoid having both S and R active simultaneously, or b) if you allow S and R to both be active simultaneously, but you ensure that they do not both become inactive without sufficient time elapsing between the first going inactive and the second going inactive.

Answer 2

SR Latches have a static invalid state when both inputs are asserted ON.

The first to de-assert turns OFF its output Q=0 or Q#=1.

A metastable or "dynamic race" or race condition must also be avoided to prevent illegal states where Q=Q#=1 when both inputs are coinciding 0 to 1 and 1 to 0. Datasheet setup, and hold times will guarantee valid logic if used properly using the DFT modules.

So they aren't bad registers and do use fewer transistors than D FFs, but they must not be misused.

play here click L or H inputs