I have always read that delays declared in RTL code can never be synthesized. They are meant only for simulation purpose and modern synthesis tools will just ignore delays declarations in the code.
For example: x = #10 y; will be considered as x = y; by the synthesis tool.
What are the reasons delay declarations in any hardware description language (for example, VHDL, Verilog or Sytem-Verilog) cannot be synthesized?
Synthesizing means somehow converting what you have described (in Verilog here) into real hardware.
Now in your Verilog you say that you have a 50ns delay. Ok, but now, in term of hardware, how would you convert this into actual hardware?
If you are using an FPGA, how would you actually build your 50ns delay using the available FPGA resources (LUT, Registers, Ram element, ...)? By adding additional routing delays? imagine that you specify 1s delay! Impossible without using ALL the routing capability of your chip (maybe not enough). Your design can't be fitted. Same for an ASIC. You would use 80% of the silicon surface to add a delay to ONE line.
The way is it supposed to work is that you use synchronous design and you implement the delay by yourself using counters or other techniques. But delays have to be multiples of the clock of that element.
Usually you find things such as "after 10 ns" theses are propagation delays. When doing an ideal simulation on a Verilog simulator, outputs happen exactly when the inputs change. This is not realistic and does not describe the way real hardware work. To account for that you can specify after how much time your output will be changed: using the delay declaration.
Porting my answer from SO. Which focuses on why it is impractical to synthesise absolute delays
When synthesising clock trees the synthesis tool balances these by adding delays so that all nodes receive the clock at the same time, so it would seem that the synthesis tool does have the ability to add delays.
However when ASICs are manufactured there is a variance in speed, at a high level this can be viewed as Slow, Typical and Fast. In practice there are hundreds of variations of these corners where certain types of device in the silicon run fast and others slow.
These corners of the silicon also have a temperature rating, worst case may be +140C Fast silicon and -40C Slow silicon. The variation of the delay through a buffer in this case could be from 1ns to say 30ns.
To bring this back to Verilog if #10 was synthesisable you would actually get 155+-145 ie 10ns to 300ns, if you have also designed something with #20 to be part of the same interface or control structure it is going to have a range of 20ns to 600ns. Therefore the whole thing is not really valid against your design. You do not get the exact #10 and #20 that were specified.
The clock trees are designed in a way to cap the max and min delays and so that all nodes on the clock tree will scale relative to each other. They are never given such a strict rule that it must be #10ns as this is physically impossible to guarantee in a combinatorial circuit.
The only absolute unit of time would be from an external clock. Where would the arbitrary delay come from - what sort of discrete digital logic equivalent would produce it from the clock?
If you want a synthesisable delay then you will need to use the external clock input and an appropriate state machine/counter that will count for specific number of clock cycles.
