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I have a question about the intel x86 instruction CVTTPD2PI mm, xmm/m128.

In Intel(R) 64 and IA-32 Architectures Software Developer's Manual Combined Volumes: 1, 2A, 2B, 2C 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C, 3D, and 4 Order Number: 325462-080US June 2023.

Though there is a CPUID Feature Flag column for the other instructions, the instruction of this question does not have that column. However, since it uses an mm register and an xmm register, I think CPUID of MMX and/or SSE is required at least.

The same problem exists for "MOVDQ2Q mm, xmm".

I want to know about a CPUID required to use this instruction.

(P.S.1) I think CVTTPD2PI is an SSE2 instruction since other sections have some descriptions about it, but the instruction table does not have a CPUID flag column.

(P.S.2)

A Page for "MOVDQ2Q mm, xmm" has the following :

Protected Mode Exceptions
#NM If CR0.TS[bit 3] = 1.
#UD If CR0.EM[bit 2] = 1.
If CR4.OSFXSR[bit 9] = 0.
If CPUID.01H:EDX.SSE2[bit 26] = 0.
If the LOCK prefix is used.
#MF If there is a pending x87 FPU exception.

"If CPUID.01H:EDX.SSE2[bit 26] = 0." means that it requires a bit of CPUID for SSE2 is set.

(P.S.3) I found the following site using Google with "SSE2 instructions" : https://docs.oracle.com/cd/E18752_01/html/817-5477/epmpv.html It has a list containing CVTTPD2PI and MOVDQ2Q.

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    According to this guide from Intel, it should be sufficient to check for SSE2 support. intel.com/content/www/us/en/docs/intrinsics-guide/…
    – Simon Goater
    Commented Jul 7, 2023 at 11:43
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    @SimonGoater: That would make sense. It deals with double-precision in XMM regs, so it wouldn't have been part of SSE1. But it's also dealing with MMX registers, so is probably a pretty old instruction. SSE2 was the first SSE extension to handle double-precision FP at all. Also the first to include SIMD-integer instructions on XMM regs, so it makes some sense that MOVDQ2Q wouldn't be introduced until then, although I would have guessed SSE1 if not for that table of exceptions showing that it requires SSE2. AMD's manuals might be useful if they show SSE feature levels for CVTTPD2PI.
    – Peter Cordes
    Commented Jul 7, 2023 at 13:09

1 Answer 1

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Yes, CPUID leaf1 EDX[SSE2] is correct. The two images below are from the AMD programmer's manual(Vol 5 64-Bit Media and x87 FP instructions). The second table shows a #UD on CVTPD2PI if CPUID.1.EDX[SSE2] = 0.

CVTPD2PI Instruction description

CVTPD2PI Exception Information Table

In the Intel PRM Vol 1 Chapter 11 contains an overview of SSE2 instructions. CVTPD2PI is discussed under the sub-section SSE2 Conversion Instructions In section 11.1 (Overview of SSE2 extensions) this statement appears: If CPUID.01H:EDX.SSE2[bit 26] = 1, SSE2 extensions are present.

Combining all the above information from AMD and Intel manuals, I think you are correct in your understanding that CVTPD2PI is enumerated via the SSE2 feature bit of CPUID leaf1.

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  • do not use images, just text
    – Bartosz
    Commented Jul 26, 2023 at 11:27

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