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Questions tagged [intel]

For issues related to Intel semiconductor chips and assemblies, Intel architectural features and ISA extensions, and Intel chips micro-architecture.

0 votes
0 answers
33 views

Alder Lake N - UEFI GPIO Register Defaults/Initialisation

I purchased an obscure NAS only sold to the Chinese domestic market (Zspace Z4Pro) with a view to using another OS on it since it was intel based (i3-N305) For reasons unknown the power to the drive ...
Whiterat's user avatar
0 votes
0 answers
11 views

ax201, ax211 wifi and Bluetooth card upload speed too low [closed]

I recognize in my pc with that cards the upload speed is very low (1-2 Mb/s), and my optical connection is symmetric 1000 Mb/s. And I find the reason but I don't know the solution. ...
Zsolt Oskar Asboth's user avatar
1 vote
0 answers
43 views

Alder Lake N - ACPI/DSDT - GPIO - Change default value

I purchased an obscure NAS only sold to the Chinese domestic market (Zspace Z4Pro) with a view to using another OS on it since it was intel based. I can boot and run another OS (ESXi/Proxmox/etc) fine ...
Whiterat's user avatar
0 votes
0 answers
64 views

How to use intel TCO watchdog with iTCO_wdt?

I have an intel platform (Alder Lake N50) and I'm trying to use the chipset watchdog hardware. My kernel is configured to have the iTCO_wdt module, when I insert it, the device is detected and /dev/...
zzi's user avatar
  • 98
1 vote
0 answers
54 views

Copying differently contiguous arrays vs same contiguity arrays

I'm observing different speeds on different machines, but couldn't reason why. Please help me find the reason behind this and how one can handle this difference in performance-critical code - running ...
Vedaant Arya's user avatar
4 votes
0 answers
60 views

Why does Intel x86 manual use +rd instead of +ro or +rq for 64-bit registers?

The description of the PUSH instruction in the Intel manual (PDF, Volume 2, Chapter 4.3, PUSH) contains the line 50+rd PUSH r64. It seems +rd is used throughout most of the instruction descriptions ...
user2468852's user avatar
0 votes
2 answers
73 views

How exactly x86 processor fetches the first instruction from SPI flash memory

On a x86 processor upon power ON of the system , the first instruction the processor usually execute is at 0xFFFFFFF0 which is called reset vector. Typically this address is in the BIOS or flash ...
shivakumar's user avatar
0 votes
0 answers
31 views

Intel IGCL API. cltinit always returns CTL_RESULT_ERROR_INVALID_NULL_HANDLE

I just started with this API and try to run examples. Unfortunately ctlinit always fails with CTL_RESULT_ERROR_INVALID_NULL_HANDLE ctl_init_args_t CtlInitArgs; ctl_api_handle_t hAPIHandle; ...
0___________'s user avatar
0 votes
0 answers
16 views

Intel Ethernet Network Adapter E810 Inventory Data Query

I want to query the E810 NIC Card whether it containes GNSS Mezzanine card. Is there any command to query the GNSS module on it? I have tried to get the related information by using "lshw" ...
burhansunbul's user avatar
0 votes
0 answers
33 views

Intel IPP Illegal value for border type

The following code snippet reads a JPEG file into memory, does Cubic resize halfing by 2 with Intel IPP and then writes the resized memory blob into a different JPEG file. #include <stdio.h> #...
aculnaig's user avatar
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0 answers
20 views

Android Emulator crashes after installing Android Emulator hypervisor driver (AEHD)

I work on a Dell laptop with Windows 11 and use VSCode for programming. For the past few weeks, I've been having serious issues with the Android emulator, which sometimes crashes and causes the PC to ...
Azaria77's user avatar
0 votes
0 answers
12 views

Undefined reference Intel IPP with CMake [duplicate]

CMakeLists.txt cmake_minimum_required(VERSION 3.5) # Set IPP root directory set(IPP_ROOT_DIR "/opt/intel/oneapi/ipp/2021.11") # Specify the directory containing the FindIPP.cmake file set(...
aculnaig's user avatar
0 votes
0 answers
22 views

Problem with setting up Page Attribute Table (PAT) under Jailhouse hypervisor on a x86 Intel Xeon system

I am trying to setup the Jailhouse hypervisor on an Intel Xeon x86_64 system. However, the hypervisor gets stuck when writing to the MSR_IA32_PAT during the initial setup. Apparently, the value that ...
Syed Aftab Rashid's user avatar
0 votes
1 answer
39 views

Compiling with instruction set extensions

From my understanding, when I compile in Visual Studio for x64, it is using some baseline version of the x86-64 ISA. Newer instruction sets from Intel have been supersets of old ones, so if I want to ...
Levi's user avatar
  • 23
1 vote
0 answers
61 views

The hardware decoding was successful, but the hw_frames_ctx in the received frame is empty

I tried to use QSV hardware decoding under ffmpeg, using the integrated graphics 730 on my computer. Here's the code I used to initialize the decoder const AVCodec* codec = NULL; int ret; int err = 0; ...
mercuric taylor's user avatar

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