Questions tagged [x86]
The term x86 denotes a family of backward compatible instruction set architectures based on the Intel 8086 CPU. From Wikipedia: http://en.wikipedia.org/wiki/X86
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Branch Prediction: How does a correlative branch predictor select from the global history?
I am trying to understand how branch prediction works, specifically with regards to correlative branch prediction. I understand that in an (m, n) branch predictor, there are m branch predictors, with ...
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Where on the 64bit memory of a PC would one byte end up?
I have a simple question I think.
A typical pc with ram has a 64bit databus between the cpu and ram. Let's say the ram starts at address 0, and I write i byte to address 0. Now my question is, would ...
user369697
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Why is the data for an x86 GDT entry designed this way?
I wanted to learn more about systems and so I was reading about x86 global descriptor tables for memory segments as one does, and I came across this table from here:
I think I understand why all the ...
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Modify a binary and account for relative jumps
Most binaries have jump and control flow instructions that are relative to other locations in the binary. For example: if I modify an instruction around 0x12341232, and there is an instruction ...
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Is it dangerous to link together -mno-red-zone and regular code?
I know that in x86_64, there exists a 128 byte red zone above (or below, address-wise) the stack pointer that functions can use without subtracting from rsp.
This sounds to me like the only things ...
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What is meant by /0 in AMD64 specification?
The AMD64 specification talks about /0 with regards to instruction encoding but I don't have a clue what is meant by that. For example, in Volume 3 the ADD instruction has three forms:
ADD reg/mem16,...
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Registers and Stacks in NASM
So, I am more or less voluntarily learning NASM, and I have problems finding sources that really explain it. Unlike with Java or C# I can't just use google as well, since Assembly just isn't used by ...
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How to align on both word size and cache lines in x86
From what it sounds like, a 64 bit processor means aligning to 64 bits, which means if you have unicode utf-8 stored in there, each 8-bit chunk would take up 64 bits of space. That doesn't really make ...
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What tasks does a memory barrier enforces other than preventing the re-ordering of instructions?
I know that a memory barrier prevents the re-ordering of instruction from before to after and from after to before the memory barrier, for example if I have the following instructions:
instruction 1
...
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How does x86 deal with register pairs?
I’ve been reading about older processors (8080, 8086 and that) and i’ve seen that those older 8-bit processors had some 16-bit instructions through the use of register pairs. For example, on the 8080, ...
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How does a CPU load multiple bytes at once if memory is byte addressed?
I've been reading about CPUs and how they are implemented, and some big complex architectures (looking at you x86) have instructions that load from memory during one clock cycle. Since one address ...
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Why data alignment is used exactly?
Each data type must be aligned to a multiple of some number of bytes, for example a short int must be aligned to a multiple of 2 bytes, and an int must be aligned to a multiple of 4 bytes.
But why ...
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Intel Memory Addressing Form
I'm am trying to understand machine code memory addressing for x86, and I've encountered two opposing general forms for addressing (using the ModRM and SIB bytes).
Most unofficial resources I consult ...
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Make multithreaded program asynchronous
There is an application that processes TCP/IP requests according to some logic, and pretty always it connects to DB.
Architecture is very common: one client -> one processing thread -> one DB ...
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The difference between accumulator-based and register-based CPU architecture?
I don't understand the difference between an accumulator-based CPU architecture and a register-based CPU architecture. I know x86 is register-based but it has an accumulator-like register. I only ever ...
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