Questions tagged [stack-up]
The stack-up tag has no usage guidance.
71
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Layer stack up selection for better signal integrity
I need to find an optimized stack up from the signal integrity point of view. I want provide for all of my signal tracks an adjacent GND plane. I have the following candidates for my stack up, would ...
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Layer stack up and impedance matching- 100 ohm
I have a 14 layer stack up as follows (the stack up is from EURO circuit):
I need to provide 100 Ohm differential impedance for my LVDS on layer 7, currently by the information from the manufacturer (...
- 511
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Gerber files sequence [closed]
I have the following Gerber files from the manufacturer for order confirmation. As I inspected them, I have inferred that the order of the copper layers from top to bottom are tl, l3, l2 and bl. But ...
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2
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4 layer stackup with space constraints
I am a student and this is my first time doing a PCB. I am wondering if it's more optimal to designate both ground planes with the same net, or have them as DGND, AGND, and use a net tie.
I have a ...
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What is the best 4-layer stack-up for lowest EMI susceptivity?
I plan to design a 4-layer board that will work on an industrial machine. This machine has AC motors driven by commercial AC drives on it. Since the earth ground is very weak at the place, they ...
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JLCPCB Solder Mask Parameters for 4-Layer Impedance Controlled Stackup
I am a bit confused by the solder mask parameters, offered by JLCPCB on their Impedance Control page.
There you can find "Coating Above Substrate C1", "Coating Above Trace C2", &...
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2
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316
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PCB Build-Up and Stack-Up alternative for 8-layer PCB
I am looking at an open-source design for an NVIDIA Jetson Nano carrier board made by a company called AntMicro. See here
The design is an 8-layer design with the following Stack-Up and Build-Up ...
- 33
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127
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Tight GND plane Pros and Cons
Imagine a typical 2Oz/1Oz, 4 layer PCB with a stack-up, Sig/Pwr, GND, GND, Sig/Pwr. Your typical trace width/space would be 0.2mm/0.2mm, and a prepreg Dk of ~4, ignore the Core. Fastest signal on the ...
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For a 6 layer PCB, what difference does it make if we use a CPCPC vs a PCPCP? (C is for core and P for prepeg)
I am working on a 6 layer PCB for motor control applicatin using Altium and the stackup being used is as follows:
Sig
GND1
PWR
Sig
GND2
Sig
I am little confused regarding the correct order of core and ...
- 43
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83
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4 Layer PCB stackup (components on both sides)
I am in the process of designing a 4 layer PCB (components placed on both sides) with some specific constrains. I need to use the top layer as Ground plate and bottom layer as a signal layer. The ...
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Altium Layer Stackup - Not Loading Sierra Circuits Layer Stackup Export
First post. I am trying to load an exported XML file from Sierra Circuits:
When I go to my Layer Stackup page in my project, then I go to File>Load Stackup From File...
And it does not show any ...
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1
answer
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6-layer stack up: Optimal core/prepreg thinkness and coupling to GND
I'm designing my first 6-layer board using a SIG|GND|SIG+PWR|SIG+PWR|GND|SIG stack up. This is often claimed to be the best stack up online and in literature ...
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3
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641
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PCB design for high-frequency differential lanes (PCIe and USB)
I have designed an M2 adapter which converts from KeyE to KeyM.
Practically this means my board can be inserted into a KeyE slot, and it can host a KeyM SSD.
Gray rectangle is the KeyM socket on my ...
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2
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611
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6 layer PCB stack up and routing strategy
I have a couple of questions about the stack up and routing strategy in a 6 layer PCB.
I'm in the situation where all the important chips are on the top layer, so all the important tracks start and ...
- 828
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Optimal 4-layer stack up for high-density board
I have a question about designing a stack up for a 4-layer PCB with a high-density top layer. I know the optimal way to generally do this is to go for either 1 or 2 as these stack ups provide a good ...
