All Questions
4
questions
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43
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Can we service another memory request from L1 cache when an L1 miss is being serviced from L2?
Consider the case where L1 cache miss occurred and is being serviced by L2 cache which could take many cycles (may go to main memory in case of L2 cache miss). In the meantime L1 cache is idle, in ...
- 137
1
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103
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Finding RAM product/solution for tiny embedded linux system (<1GB)
I'm finding it quite difficult to navigate among the copious memory solutions available when selecting a RAM solution for a tiny embedded system I'm developing.
I will run an OS such as PetaLinux on ...
- 91
1
vote
1
answer
130
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If a SoC is given more memory then it is able to use, how does it deal with that?
Say it can only use 2GB's, and is provided 4, does it only use half, or not use any of the ram?
- 47
0
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1
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324
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CPU ports and cache controllers
I have seen CPUs conforming to Harvard architecture with dedicated ports for program memory and data memory. I have also seen that instruction and data caches (read-through caches) are connected to ...
- 187