All Questions
24
questions
0
votes
1
answer
123
views
Serial signal too slow for FPGA serdes
I have a serial signal coming from a fiber optic transceiver at 200Mbps, but the serdes on the Ecp5 fpga that I want to use only supports signals as slow as 270Mbps. Between clock recovery, serdes, ...
3
votes
0
answers
118
views
Mid-bandwidth data and power over coax
I am interested in transmitting both digital data and power over a single coaxial cable between two FPGAs. Communication should be at least half-duplex. Communication speed should be on the order of ...
0
votes
0
answers
45
views
Serial I/O Not working on DE5-Net
I'm porting a circuit from DE0-Nano to DE5-Net.
I'm currently implementing a simple test circuit for the DE5-Net. So far I can program the user LEDs and the two Hex Displays.
However, I don't seem to ...
1
vote
1
answer
120
views
Write into external registers from FPGA
I want to initialise a register of an external component with a FPGA. The data is latched by the external component at every falling edge of the clock signal.
You can see in the diagram that the SDATA ...
5
votes
2
answers
1k
views
Best board-to-board low latency protocol/interface
I've been asking similar question which received some downvotes, so I'm reformulating my task (hopes this one gives more clarity).
I'm planning to establish a high-speed (3 Gpbs full duplex) serial ...
0
votes
1
answer
161
views
Several MIDI over USB Device
I'm looking at creating a "specialized" MIDI over USB device for a project I'm working on and my requirements have gone beyond that of the Arduino/Pi/etc, due to limited I/O. I am very much a beginner ...
0
votes
0
answers
516
views
Convert parallel LVDS to csi-2
I have a camera outputing parallel data and I want to interface it with iMX6 module which accepts CSI-2 camera data.
Are there any ready & cheap solutions to convert parallel into CSI-2.
Lattice ...
0
votes
1
answer
541
views
deserializing high speed data
I am trying deserialize data that come out of a LM98640 into 14 bits words:
Attached you can find a figure of the signals out of the LM98640.
http://www.ti.com/lit/ds/symlink/lm98640qml-sp.pdf
(...
2
votes
2
answers
506
views
developing simple serial link on FPGA
I am trying to develop a digital data link based on FPGA (spartan 3E) where the transmitter serializes 8 bit parallel input to single channel. At receiver side I want to get the data back by de ...
5
votes
2
answers
2k
views
What does the FPGA do with unreferenced I/O pins?
Here's one thats been puzzling me for a while.
I have an FPGA design in Altera, driving an audio chip and programmed through its serial interface. I monitor and debug this with an oscilloscope/...
2
votes
3
answers
819
views
DE0-nano I/O with TTL cable
I'm currently working on a project about I/O with FPGA. I am using TTL-232R-3v3 cable for serial communication between my laptop and DE0-nano. I want to know if it is possible to send a signal on RX ...
6
votes
2
answers
866
views
Is anything besides rx and tx actually used in rs232 nowadays?
Whenever I come across a PIC or even a FPGA project that is communicating over the serial port with a PC; only Rx, Tx and power are connected on the 9 pin connector and the other pins/signals are ...
3
votes
1
answer
83
views
Help with multiple receiver channels and single storage architecture
I want to build a datalogger that has multiple receiver channels that run on serial communication protocol RS232 and then collect the information from the channels in a single storage that would be ...
6
votes
5
answers
11k
views
UART Receiver Sampling Rate
I am trying to create a UART receiver in Verilog for my FPGA. I was following this guide http://www.fpga4fun.com/SerialInterface4.html
According to it the standard practice for asynchronous ...
1
vote
1
answer
588
views
FPGA; reconfigure from SPI flash
I have designed a Xilinx Spartan-6 PCI card with SPI configuration interface (please check Figure 2-12 of ug380.pdf user guide). I can program the serial flash through JTAG cable, I can also modify/...