All Questions
20
questions
3
votes
1
answer
53
views
Voltage drop in NMOS inverter with enhancement load
In the enhancement load NMOS inverter, why is the voltage drop across M2 at least equal to Vth when VIN is low ?
Is it because for M2 when VIN is low the voltages VGS = VDS, so VDS > VGS - Vth and ...
- 63
3
votes
3
answers
149
views
Is it always given that ground has lower resistance than output even If output is far closer in an inverting nmos? [closed]
Currently I'm learning about MOSFETs (N-MOS and P-MOS) --basically how a transistor works. My question is why does the current always prefer the grounding output even though it is further away than ...
- 31
0
votes
1
answer
245
views
the inverter switching point
As we know the mobility of the "nmos" device is 3x greater than "pmos", and when we want to correct the switching point of an inverter for vdd/2 we usually change the W of the &...
4
votes
1
answer
214
views
LTspice Half bridge current spikes
I simulated a half bridge with two NMOS and at every switching event a current spike up to 1.2 A in the voltage source V4 occurs. I used a resistor as load because with any inductive or capacitive ...
- 147
0
votes
1
answer
68
views
How should I correct this NMOS static inverter?
So in my notebook I have this circuit scheme for a NMOS static inverter:
Vi is the input
Vo is the output
VDD is the voltage source
It is obvious that the M2 MOSFET will never turn on. Is the circuit ...
- 61
0
votes
0
answers
1k
views
How does the CMOS Schmitt trigger work
I have some questions on how the schmitt trigger works.
Assuming we start with low Vin hence Vout is high. It means that M1 is ON thus the source of M2 is conducting Vdd hence M2 is On as well. ...
- 17
0
votes
1
answer
193
views
Measuring switching time of 5LN01SP (NMOS)
I am working on switching time test circuit for 5LN01SP specification.
This is my circuit:
Input test signal is (as per specification) a pulse of 1kHz frequency:
PW = 10us
D.C. == 1%
We can see the ...
- 236
0
votes
0
answers
30
views
Performing switching time test with NMOS (5LN01SP)
I am about to feed my switching time test circuit with input signal from signal generator. In a 5LN01SP's specification input test signal is marked as:
PW = 10us
D.C. <= 1%
(see the picture)
It is ...
- 236
0
votes
2
answers
1k
views
Output impedance of a logic inverter using an NMOS
I have drawn below an NMOS logic inverter and its equivalent circuit for HIGH state:
Why is this gate said to have high output impedance at HIGH state? Is that because of the open switch or because ...
- 2,217
2
votes
4
answers
2k
views
What is the use of pull-down networks in CMOS gates?
Below you can see the basic CMOS inverter. What I don't understand about this particular design is the purpose of the n-channel mosfet which is the part referred as pull-down network.
What if we ...
user183701
0
votes
2
answers
341
views
How to redesign the circuit such that the switching threshold is VDD/2.
he switching threshold is the input voltage where the output crosses VDD/2. I want to redesign the circuit such that the witching threshold is VDD/2.
1
vote
1
answer
2k
views
Effect of changing the length of an inverter's N-mos transistor on the propagation delay
let's say we want to check the time it takes for our source Vdd to charge a capacitor through an inverter network. changing the width of the P-mos transistor will make more current flow, thus ...
3
votes
2
answers
11k
views
Inverter VTC , VOH and VOL definitions
I am confused in definitions of VOH and VOL in VTC of inverters. My textbook says this graph:
but shouldnt the y value corresponding to VIL be VOH and y value corresponding to VIH be VOL OR Is VOH ...
user98208
0
votes
2
answers
5k
views
pseudo nmos inverter
i was tring to analyse pseudo nmos inverter but seem to be struck. The pmos above which is grounded will always be in triode region right coz v sd<|vov|? so what will be the R be as shown in my ...
user98208
1
vote
1
answer
348
views
Effect of increased leakage of PMOS in reversed inverter configuration
I have built the standard CMOS inverter in reversed configuration by putting NMOS on pull up side and PMOS on pull down side. This will work like a buffer but the the upper and lower bound of the ...
- 33