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Questions tagged [multicore]

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Issue with Running Two Separate Codes on Intel Cyclone V SoC ARM Cortex A9 Dual Core via QSPI

I am working on an Intel Cyclone V SoC ARM Cortex A9 Dual Core setup and aiming to execute two distinct codes on Core 0 and Core 1 in bare-metal mode. While I've successfully executed this setup using ...
Support's user avatar
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0 answers
157 views

Assistance Needed: Trouble Running Bare-Metal Code on second core in Cyclone V SoC

I am working on intel cyclone 5 hps I have two cores in a processor Core 0 core 1, I want two code to run on two different cores core 0 and core 1 in bare metal. When I run in jtag mode it works, for ...
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0 answers
81 views

ESP32 Dual Core

Does anyone have experience with using the second ESP32 core? I searched the internet but I only came across two loops that run independently of each other. I would need to be able to call a function ...
Kabl62's user avatar
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0 answers
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Bare metal STM32H755 (dual core) programming - Code won't start running

I just bought a STM32H755ZI Nucleo board after having toyed with the Nucleo F411. The problem I'm facing is: When I flash the program into the micro-controller and debug, it seems as if I couldn't ...
Juan_David's user avatar
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1 answer
114 views

Multicore CPU design dilemma on reading from/writing to hardware devices

I have built a simple 8-bit processor with 16-bit address lines and 8-bit data lines; not the most efficient CPU architecture, but it does the job. As you might have guessed, this CPU is really simple:...
gmmk's user avatar
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0 answers
78 views

How to build a system with two multicore microcontrollers?

I am thinking about building a system that utilizes two microcontrollers that communicate with one another. Currently, I am looking into using two stm32 microcontrollers. They have two cores and I ...
user16824253's user avatar
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0 answers
87 views

ESP32 DEVKITV1 - Can't generate waves in two cores

I'm using a ESP32 (DEVKITV1) to generate two waves in two different cores. Below is the code I'm using. ...
RafaelSantiago94's user avatar
0 votes
2 answers
158 views

CPU (core) all located in close proximity. A coincidence or by design?

I've noticed pictures of decaped IC chips and noticed that CPU (cores) found on die are all located close together. Is there a reason for this or is it just a coincidence? If it is not a coincidence ...
JoeT's user avatar
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10 votes
7 answers
2k views

Why do modern processors use few advanced cores instead of many simple ones or some hybrid combination of the two?

I understand that memory is a big bottleneck in modern computer systems, but can't a system with many simple cores be more efficient than one with single digit number of advanced cores for some tasks? ...
Isaac Dorfman's user avatar
1 vote
0 answers
101 views

ESP32 Neopixel acting strange when using dual core functionality

I have just started using ESP32 and tested dual core functionality, which works fine i.e. can blink two leds with different blink intervals parallelly. Also I've tested touch sensors, they also works ...
Rishabh's user avatar
  • 153
0 votes
1 answer
120 views

Did the Multicore Association go out of business?

I am working on a project with the ADSP-SC58x from Analog Devices which uses Multicore Communications API (MCAPI). As I am trying to gain more information about the API and standardization itself I ...
Johannes's user avatar
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1 answer
71 views

guesstimate max current of a domestic appliance

The appliance is a quartz oven, 1000W @ 250V. I am trying to obtain a max transient figure for the current (no oscilloscope on my bench). Opened the oven and checked the writings on various parts - ...
kellogs's user avatar
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0 votes
1 answer
840 views

Why disable interrupt is time-consuming in multi-processor computer?

I have a book statement: Disabling interrupt is time-consuming in multi-processor system. I suspect that this is related to the hardware implementation of how interrupt is enabled/disabled. So ...
Kindred's user avatar
  • 221
7 votes
3 answers
5k views

Is it true that on a modern processor, parallelism is possible on a single core?

Final Edit: I just realized that when use the word "parallelism", it's almost parallelism==ILP, I originally thought even a single instruction could be divided into ...
Kindred's user avatar
  • 221
1 vote
1 answer
280 views

Multicore ARM how to assign a critical task to one dedicated core [closed]

Suppose I have a multicore ARM processor (to make it simple assume 2 cores with an unshared cache between the 2 cores). Suppose my system contains a critical task and several non-critical tasks. ...
S12000's user avatar
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