Issue with Running Two Separate Codes on Intel Cyclone V SoC ARM Cortex A9 Dual Core via QSPI

Question

I am working on an Intel Cyclone V SoC ARM Cortex A9 Dual Core setup and aiming to execute two distinct codes on Core 0 and Core 1 in bare-metal mode. While I've successfully executed this setup using JTAG debugging, where I sequentially debugged Core 0 followed by Core 1 after taking it out of reset, I'm encountering a problem when attempting to run both cores via QSPI flash.

Despite combining both programs into a single image file, Core 1 fails to execute as expected. In the linker/scat file, Core 0's entry point is specified as 0x60000, and Core 1's entry point is set to 0x9fff0. However, upon execution, Core 0 behaves correctly, while Core 1's program counter jumps to 0xFEBAF5E8 instead of its designated entry point.

Your insights or suggestions on resolving this discrepancy would be greatly appreciated.

Thank you!

Core 0 firmware and linker file

#include "HAL/hal_common.h"
#include "HAL/hal_timer.h"
#include "alt_mmu.h"
#include "alt_cache.h"
//#include "hwlib.h"

typedef int32_t             ALT_STATUS_CODE;

#define ARRAY_COUNT(array)  (sizeof(array) / sizeof(array[0]))

#define RSTMGR_MPUMODRST_OFFSET 0x10 // offset
#define RSTMGR_MPUMODRST_ADDR (0xFFD05000 + RSTMGR_MPUMODRST_OFFSET)

#define RSTMGR_CPU1_ADDR 0xFFD080C4
void main(void)
{
    // Initialize HAL
    HAL_Init();
    TIM_Init();
    TIM_Preset();
    volatile uint32_t* cpu1startaddr = (uint32_t*)0xFFD080C4;
    *cpu1startaddr = 0x9fff0 ;   // cpu1 reset exception address 0x160010

    //*pPreLoaderStateReg = BL_CONFIG_PRELOADER_STATE_VALID;
    uint32_t reg_val = *(volatile uint32_t *)RSTMGR_MPUMODRST_ADDR;
    reg_val &= ALT_RSTMGR_MPUMODRST_CPU1_CLR_MSK;
    *(volatile uint32_t *)RSTMGR_MPUMODRST_ADDR = reg_val; // taking core 1 out of reset from core 0

    while (1)
    {

            // functionality we want to achieve from core 0 also it take core 1 out of reset already

}

}

Scat file

SDRAM 0x00060000 0x40000
;0x40000
; 0x62250
{
    ; Vector Table
    VECTORS +0
    {
        * (VECTORS, +FIRST)
    }    
    
    ; Application Code
    APP_CODE +0
    {
        * (+RO, +RW, +ZI)
    }
    
    ; 256 Byte stack
    ARM_LIB_STACK +0 EMPTY 0x0100
    { }  
    
    ; 64kB Heap (not used)
    ARM_LIB_HEAP +0 EMPTY 0x010000
    { }    
}

Core 1 firmware and linker file

#include "HAL/hal_common.h"

//#include "HAL/hal_timer.h"

/**
 * Bootloader Main Function
 */
void main(void)
{
    HAL_Init();
//  TIM_Init();
//  TIM_Preset();
    uint32_t   ii=0;
    uint8_t    led_status=0;
    while (1)
    {
        // functionality we want to achieve from core 1
}
}

Scat file

SDRAM_CORE1 0x9fff0 0x6c960

{
    ; Vector Table
    VECTORS +0
    {
        * (VECTORS, +FIRST)
    }    
    
    ; Application Code
    APP_CODE +0
    {
        * (+RO, +RW, +ZI)
    }
    
    ; 256 Byte stack
    ARM_LIB_STACK +0 EMPTY 0x0100
    { }  
    
    ; 64kB Heap (not used)
    ARM_LIB_HEAP +0 EMPTY 0x010000
    { }    
}