All Questions
Tagged with impedance-matching pcb
32
questions
1
vote
1
answer
122
views
Routing traces underneath impedence controlled traces in 4 layer PCB
I am working on 4-layer PCB with following stack-up:
Layer-1 Signal traces
Layer-2 Ground
Layer-3 Ground
Layer-4 Signal + Power traces
The PCB contains ESP32-S2 MCU with USB and chip antenna. I ...
- 45
2
votes
2
answers
241
views
Impedance matching from PCB to cable
I am designing a PCB board connecting to a 2 meter long cable with 75 Ω impedance. I have an output buffer amplifier at the output of the PCB.
For the buffer op amp with 0 output impedance, should I ...
- 33
3
votes
1
answer
272
views
Why does a 4 layer PCB board significantly reduce the trace Width needed for a 50 ohm transmission line when compared to a 2 layer PCB board?
I am designing my first 50 ohm impedance trace on a PCB that connects to a single wire antenna. I was playing around with JLCPCB's impedance calculator and I noticed a significant reduction in the ...
- 1,072
0
votes
0
answers
35
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Differential pair for Ethernet on Olimex boards
Just out of curiosity I was looking into ESP32 based boards such as EVA, GATEWAY, POE, POE-ISO by Olimex and found the differential pair used for Ethernet is all different sizes (i.e.: width and space ...
- 176
1
vote
1
answer
139
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Possible to separate D+ and D- on 2 layer board?
I am trying to make a PCB adapter, where the connections are USB-C, so need to cross connect the D+ and D- on both connectors.
Is it possible to run D+ on top layer, and D- on bottom layer?
Attached ...
- 444
0
votes
2
answers
748
views
6 Layer PCB 50 ohm Impedance Matching
What information do I need from the PCB manufacturer to create a 50 ohm impedance trace on my 6-layer PCB?
- 111
0
votes
1
answer
650
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Doubt about 50 ohm impedance calculation
I am developing a 4-layer FR-4 board containing a GNSS receiver (L1 + L2). RF tracks must have an impedance of 50 ohms. The board contains two inner layers of GND and a ground plane around the RF ...
- 135
2
votes
1
answer
622
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Differential Pair routing insight for USB 2.0 circuit involving a USB C connector with multiple D_N and D_P pins
I'm bringing USB 2.0 into a PCB design from a USB C receptacle. I've already accounted for the 5.1k resistors needed but I'm stumped on how best to run a differential pair with DP1, DP2, DN1 and DN2 ...
- 23
1
vote
0
answers
58
views
Matched termination of a microstrip using absorber foam
I have open ended microstrips in an RF circuit (operation freq. 18 GHz) and they cause unwanted back reflection into the rest of the circuit.
Now, I wonder if it is possible to eliminate / reduce ...
- 13
1
vote
1
answer
43
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Would joining pads of a pi-filter eliminate impedance changes from line to pad? Would it cause problems with alignment during reflow?
This is a 2 part question:
Would joining the pads, such as on the lower pi-filter pictured, cause any problems with alignment of the components during reflow soldering?
Would joining the pads result ...
- 543
10
votes
2
answers
2k
views
Why is length matching performed with the clock trace length as the target length?
Length matching is performed mainly to avoid the skew generated among the parallel data lines/data bus width.
All the high speed PCB design guideline suggest performing length matching with the clock ...
- 285
0
votes
0
answers
86
views
How to deal with simulation/measurement discrepancies of simple RF circuits (e.g. matching) without access to expensive equipment?
Designing a circuit (PCB) operating at low frequencies is fairly straight forward. However, my design includes a simple RF frontend. The frontend consists of usual componenents on a PCB (SMA connector,...
- 1,326
0
votes
0
answers
133
views
Can I debug this simple circuit without VNA and proper RF equipment?
I am debugging a very simple circuit (existing PCB, not designed by me) that downconverts an AM modulated signal at 900 MHz:
The problem: What I measure at "Vo" does not match my LTspice ...
- 1,326
1
vote
1
answer
166
views
What is the difference between a Line Impedance and Charecteristic Impedence?
I am thinking this from long time.
In case of Digital Circuits,
I know that, whenever a signal is incident on a PCB trace, for example, there may be an AND gate, which just switched output to 1. Then,...
0
votes
1
answer
169
views
Parallel trace signal integrity: Increasing width to match characteristic impedance vs increasing trace gap
Imagine you are routing a large number of single ended high speed traces through a long narrow gap on a PCB. Lets say these are ultra-high speed SD signals, so a 208MHz clock. The traces should be ...
- 143