Non buffered CMOS logic gates working under load when using real components (LTSpice Sim)?

Question

I'm experimenting with CMOS logic gates and have encountered something I am having a hard time understanding.

When I make an inverter using ideal components and measure the output, it works exactly as you'd expect (inverts the signal).

Then, when you load it with the LEDs, it cannot hold that voltage. Again I expected this

However now when I replace the mosfets with real models, it now works as if it was unloaded?

By default, LTSpice sets Rds to 0 for the mosfets, so the output impedance from the gate is 0. The input impedance to the LED circuit is infinitely high in comparison. For this components, Rds is in the mohms, a higher output impedance.

Based on the input/output impedances, I would expect the gate with ideal components to be fine under load (0 output impedance), and the circuit with real components to have the problem. The same thing occurs with my CMOS AND and CMOS OR gates. So why does this appear to be backwards and then do I need a digital buffer (2 NOT gates) or not?

Answer 1

Your assumption abort default models MOS is wrong. Rds will not be zero. In fact, the default Kp parameter is very very low \$K_P = 20\mu \left[\frac{V}{A^2}\right]\$ compared to the real MOSFET that was designed to work as a switch. So the default model Rds(on) for Vgs = 5V will be around \$R_{DS(on)} \approx \frac{1}{20\mu*5V} = 10k\Omega\$.

And the real MOSFET that you decided to use will have Kp parameter around \$K_P = 1\left[\frac{V}{A^2}\right]\$

Thus, for the same situation Vgs = 5V and Vgs(th) = 0.8V is will have \$R_{DS(on)} < \frac{1}{1*(5V - 0.8V)} = 0.23\Omega\$

Here you can find CD4000 series MOS models.
https://github.com/cwllau/EE_307/blob/master/CD4007%20(2).mod

  *Used in Electronics II for CD4007 inverter chip
*Note: Properties L=10u W=170u Ad=8500p As=8500p Pd=440u Ps=440u NRD=0.1 NRS=0.1
.MODEL RIT4007N7 NMOS (LEVEL=7
+VERSION=3.1 CAPMOD=2 MOBMOD=1
+TOX=4E-8 XJ=2.9E-7 NCH=4E15 NSUB=5.33E15 XT=8.66E-8
+VTH0=1.4 U0= 1300 WINT=2.0E-7 LINT=1E-7
+NGATE=5E20 RSH=300 JS=3.23E-8 JSW=3.23E-8 CJ=6.8E-8 MJ=0.5 PB=0.95
+CJSW=1.26E-10 MJSW=0.5 PBSW=0.95 PCLM=5
+CGSO=3.4E-10 CGDO=3.4E-10 CGBO=5.75E-10)
*
*Used in Electronics II for CD4007 inverter chip
*Note: Properties L=10u W=360u Ad=18000p As=18000p Pd=820u Ps=820u NRS=O.54 NRD=0.54
.MODEL RIT4007P7 PMOS (LEVEL=7
+VERSION=3.1 CAPMOD=2 MOBMOD=1
+TOX=5E-8 XJ=2.26E-7 NCH=1E15 NSUB=8E14 XT=8.66E-8
+VTH0=-1.65 U0= 400 WINT=1.0E-6 LINT=1E-6
+NGATE=5E20 RSH=1347 JS=3.51E-8 JSW=3.51E-8 CJ=5.28E-8 MJ=0.5 PB=0.94
+CJSW=1.19E-10 MJSW=0.5 PBSW=0.94 PCLM=5
+CGSO=4.5E-10 CGDO=4.5E-10 CGBO=5.75E-10)
*----------------------------------------------------------------------