Symmetric (4 terminal) MOSFET Turn-on Voltage Relative To What?

Question

As this question explains in detail, the construction of a MOSFET is symmetrical w.r.t. to the drain and source, except for the decision to connect the substrate to one of them (the reasons for doing this are described in the question). As soon as you do this, it breaks the symmetry, and that pin becomes the source, and the other pin the drain. This is done internally on all discrete 3-pin MOSFETs.

This picture is from the above linked question, before the source is connected to the p+ substrate (body):

In the case of an enhancement-mode N-channel MOSFET, when the gate-source voltage is 0V, the MOSFET is OFF (no current from drain to source). Then the gate-source rises (e.g. 3V), the MOSFET begins to turn ON.

My question is, in the case of 4-pin MOSFETs, what gate-to-??? voltage is relevant for turning the MOSFET ON, given the source is no different from the drain?

4-pin MOSFETs are not common when buying discrete MOSFETs, but in CMOS design it's common to not connect the substrate to the source to build things like analogue switches or transmission gates. In the case of an N-channel CMOS analogue switch, the substrate is normally connected to ground, and both the drain and source may be at arbitrarily higher voltages. This has the neat behaviour of being able to block signals in both directions.

Answer 1

The turn-on voltage is still Vgs (gate relative to source). It is the source and drain themselves that swap spots depending on how the transistor is biased.

For an nFET, the N-implant region at a lower voltage will be the source, and it will be able to provide electrons for the channel. When the gate voltage rises above that voltage, the channel inverts and current is permitted to flow. This means that, in your analog switch example, the gate voltage must be able to go higher than both sides of the switch, or else the channel may not be able to properly turn on for current flowing in both directions.

Throughout all of this, the P-substrate (body) in which the two N-implants are implanted must remain at a lower or equal voltage to both implants to avoid forward-biasing the implant-body junctions (drawn as diodes in your image).

Conversely, for a pFET, the P-implant at a higher voltage will behave as the source, and the channel inverts when the gate voltage falls below the source voltage. The body voltage (this time, an N-type well/substrate) must have a greater or equal voltage to that of the implants in order to avoid forward-biasing the junctions.

If you are laying out a transistor in a silicon layout package such as Virtuoso, the pcell provided by your foundry may be fully symmetric although one contact will be labeled Source and the other Drain. The simulator models and layout tools should still handle the actual device physics correctly.

It's also possible that your foundry may use asymmetric four-terminal MOSFETs. This involves things like lightly-doped drains that help with device performance and longevity, but as before, the source/drain during operation is still determined by the relative voltage of the two implants. If the transistor is operated with the source/drain swapped from the intended configuration, its performance or longevity may be compromised, but it will still behave as a MOSFET, more or less.