Proposed are mostly unrelated parameters. The MCU in particular bears no relation at all; any interference it is subject to, is the fault of poor layout, filtering and interconnection.
Note that, if nothing else, every sub-circuit can be sealed inside a metal box, with filtering applied to signals where they pass through that box, sealing any interference within. That is, shielding and filtering, at the most fundamental, should be approached topologically: there is a barrier, beyond which, a noisy sub-circuit cannot transmit, and some signals that pass that barrier subject to strict scrutiny and careful design.
A topological approach limits design scope, making filtering and control of signal quality a tractable problem. We could, in principle, consider an open circuit, a mess of spaghetti, but the interactions are strongly coupled between all connections and design is intractable even for fairly small circuits.
Filtering, of course, is subject to signal bandwidth requirements, and we would generally want at least several MHz bandwidth for something like a gate drive signal going to a switching circuit, and at least some 100s kHz for the current sense signal coming back from a switching circuit (assuming we're using the objectively best control scheme that is current-mode control). For higher-bandwidth signals, we modify the requirement to optimize signal quality: keep the signal near the box's shielding surface (inside and out), and avoid routing near heavy switching currents. Use differential techniques if necessary, so that the signal is accompanied by a reference, both subject to the same nearby fields, the same connecting impedances, the voltages of which are canceled out at the endpoint by suitable design (e.g. diff amp).
For a switching circuit, we can apply the signal quality principle directly. Consider the basic buck or boost circuit, consisting of two switches in a half-bridge configuration: there exists some physical distance between them, and thus a length scale for connecting traces/pours.
In a circuit, length means inductance.
More exactly, length means transmission lines, which we can generally take the low-frequency approximation of in switching circuits, and so we get series inductance and shunt capacitance in proportion to the impedance and length of that transmission line.
Any conductive geometry can be a transmission line, or more specifically, between any adjacent pairs of conductors can be. Most often these are traces/pours on a PCB, with respect to ground plane, or each other, and component leads with respect to each other within a component, or sometimes between neighboring components.
Thus we enhance the circuit like so:
simulate this circuit – Schematic created using CircuitLab
With waveforms like so:
Observe that, for each switching event (commutation), we have one device turning off, deadtime, then the other device turning on. In that moment, V(SW) may be high or low.
When V(SW) is high and M2 turns on, or low and M1 turns on, it is referred to as hard switching, and the full switching loss associated with Coss1 + Coss2 is dissipated.
During commutation, I(LSW) may be high or low, so that V(SW)'s capacitance is pushed around by that current, during the dead time. When this occurs in a smooth fashion, it is referred to as ZVS (zero-voltage switching): notice Coss1/2 holds V(SW) near zero while the first transistor turns off, the voltage swings until the body diode conducts, and then the second transistor turns on, its Vds already being near zero.
Here, we have ZVS at M1 turn-off and M2 turn-on.
Conversely, if I(LSW) is low, or opposite the direction required for ZVS on a given switching event, we will have hard switching, or, at best, ZCS (zero current switching). Here, we have I(LSW) low, V(SW) low, and M1 turning on, for a hard-switched event. (M2 turn-off is also ZVS, so that's three out of four total events: not bad, considering.) Note that V(SW) has considerable ringing and overshoot, and I(M1) also shows significant peak current at the same time. This ringing is due to Coss2 + LS1 + LS2 + LS3, and 500pF + 30nH is a resonant frequency of 41MHz and characteristic impedance of 7.7Ω. The ~10ns gate drive edges here are comparable to the quarter-cycle period of this ringing, so the ringing is significant and cannot be ignored in design.
These values chosen, by the way, are typical of the IRF530 shown. Roughly speaking, component lead length, trace length, etc. contribute between 0.5-1 nH per mm of length. The TO-220 package is commonly attributed as 7.5nH in the D-S path, and another 2.5nH between parts suggests they are adjacent on a PCB, and to CBYP (which, as shown, might be an electrolytic capacitor).
Exercise for the student:
Draw the equivalent circuits, at instant of turn-on, or turn-off, for the various cases: I(LSW) high or low, V(SW) high or low, M1 or M2 turning on or off.
Transform M's to switches, and reduce the circuit for any switches not changing state. Observe which Coss(1/2) are in circuit, or shorted out. Observe LS1+LS2+LS3 is always present, as the switching loop inductance. Also observe that LSW is basically a CCS during the switching event.
At last, we can address the question posed at the top:
How to determine rise and fall times of MOSFET?
We generally want to stay slower than the loop (LS + Coss) resonant period. This depends on component choice and layout/routing, so is a layout-dependent parameter. Typically, some 10s of ns can be achieved, but it depends on the components, and construction technique. Transistors on solderless breadboard with carelessly long fly leads, will incur 100s of nH between them, and switching at 100s of ns will be problematic; not to mention the mutual inductance between every loop in the circuit, sure to carry interference right back to your Arduino or whatever. With trimmed jumpers and careful layout, high 10s of ns is feasible on the breadboard, with ~100s of mV or less of common mode or conducted/induced ground noise. For more than a few amperes of load current, and certainly into the low 10s of ns switching rate, I would strongly encourage a planar construction method, whether Manhattan style over copper-clad, or a printed circuit board as such, designed with signals always above or below a solid ground plane.
We generally control switching speed by choice of gate driver, series gate resistance, and, more and more often these days as nonlinear capacitances are optimized so well, we may further need to consider negative feedback, whether in terms of current (e.g. common source inductance, ferrite bead) or voltage (shunt feedback from drain to gate, e.g. an R+C of very modest values; for the above simulation, try 10R series gate plus 100R + 22pF D-G).
Finally, note that the switching edge rates, and any ringing, determine the bandwidth of the shielding and filtering solution that we must employ to isolate this noisy section from surrounding circuitry. For edges of 10ns, a bandwidth of ~50MHz leads to a fairly easy-to-implement solution. Mind that I'm using "bandwidth" in a negative sense here: the range over which the shield/filter is effective -- the stopband.
Modern Si switches regularly emit harmonics into the 200MHz range, let alone SiC and GaN devices which can go much further (1GHz+); their shielding and filtering solutions are much more demanding!
