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I truly apologize if this question title is vague I don’t really know entirely what to ask. I’m a programmer interested in computer architecture and I’ve been reading a book about digital design. Supposedly when voltage is between Voh and Vdd it is considered a high signal. In a logic gate this would output a high signal or a “1” bit. The book didn’t do much more explaining since the aim of the book isn’t the nitty gritty math. But I’m both interested in knowing the math behind finding this voltage threshold and what each of those variables like “Oh” and “dd” represent and how they are measured!

image showing logic level thresholds

Image from: Digital Design and Computer Architecture (by Harris, Sarah & Harris, David)

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  • \$\begingroup\$ Mox, Hi. All circuits are analog, in the sense that they cannot instantly go from one voltage or current to another. Everything takes time. And there is an in-between period, during transitions from one state to another, where the signaling isn't clearly one thing or another. For example, you can look at this. The upper left corner and the lower right corner are well-understood defined states. But you can see that the signal transistions under differing loads in different ways between those areas. it's like that. \$\endgroup\$ Commented Apr 17 at 10:08

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If you read the book you lifted the image from, you'll find the items defined in section 1.6.1 and 1.6.2. VDD is the same as \$V_{\text {DD}}\$ and like wise with VOH and \$V_{\text {OH}}\$, which may be confusing you.

1.6.1 Supply Voltage Suppose the lowest voltage in the system is 0 V, also called ground or GND. The highest voltage in the system comes from the power supply and is usually called VDD. In 1970’s and 1980’s technology, VDD was generally 5 V. As chips have progressed to smaller transistors, VDD has dropped to 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V, or even lower to save power and avoid overloading the transistors.

1.6.2 Logic Levels The mapping of a continuous variable onto a discrete binary variable is done by defining logic levels, as shown in Figure 1.23. The first gate is called the driver and the second gate is called the receiver. The output of the driver is connected to the input of the receiver. The driver produces a LOW (0) output in the range of 0 to VOL or a HIGH (1) output in the range of VOH to VDD· If the receiver gets an input in the range of 0 to VIL, it will consider the input to be LOW. If the receiver gets an input in the range of VIH to VDD, it will consider the input to be HIGH. If, for some reason such as noise or faulty components, the receiver’s input should fall in the forbidden zone between VIL and VIH, the behavior of the gate is unpredictable. VOH,VOL, VIH, and VIL are called the output and input high and low logic levels.

When looking at noise margins Voh is the minimum output voltage of an output when high (and typically when sinking some current). Vih is the minimum input voltage that is guaranteed to be interpreted as 'high'. Similarly for Vol and Vil, which are maximum output and input voltages respectively- with a current being sourced.

Here is a typical CMOS gate datasheet showing those numbers. In this case 'Vcc' is used rather than 'Vdd' for historical reasons, but it means the same thing.

enter image description here

CC was used for Collector supply (NPN and positive supply assumed assumed) and DD was used for Drain supply.

74xx chips were originally bipolar, hence the Vcc. Since most chips are CMOS these days the Vdd supply actually goes to the source of P-channel MOSFETs but never mind about that. You'll also see Vss and Vee, generally used to refer to GND and negative supply respectively. You may even find chips that have something like Vee = -4.5V and Vcc = GND (ECL logic chips).

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Vdd is the positive power supply voltage.

Voh is the specified minimum value of the output (o) when the output is "high" (h).

So saying that the voltage will be between these two values doesn't tell you anything you wouldn't have known if you knew what they were. The voltage must be greater than Voh because, by specification, that's the lowest the voltage can represent a logic high. And it must be lower than Vdd because without some storage elements (capacitors or inductors) present, a transistor circuit can't produce any voltage higher than its positive supply rail.

I’m both interested in knowing the math behind finding this voltage threshold

There's no math you can do to derive Voh. It's something promised by the chip vendor in the specification for the chip.

(The chip designer, of course, had to do some math-based simulations to show the chip would meet the specification over process, temperature, and supply voltage conditions)

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  • \$\begingroup\$ Really appreciate this response, I have one last question: Does this apply to Voil as well? Is it the specified maximum voltage of the output when the output is low? Would Vdd be like my computer battery? The voltage has to be lower than Vdd because it can’t output something that’s higher than the supply right? \$\endgroup\$
    – mox
    Commented Apr 17 at 2:50
  • \$\begingroup\$ @mox, yes, Vol is the maximum specified low (l) level of the output (o). In a computer, Vdd will be determined by a power supply circuit on the motherboard, so it won't change just because the battery runs down. \$\endgroup\$
    – The Photon
    Commented Apr 17 at 3:10

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