Verilog: How do I assign multidimensional arrays as outputs in my module

Question

I am writing my Verilog module in Xilinx Vivado. I am actually dealing with 2D arrays. I want to add elements from one array to another in the following way.

For Example:

states = [[1,2,3,4], [5,6], [7,8,9]]

solution = [[2,4,3,1] , [6,5], [7,9,8]]

state_out = []; solution_out=[]

//The states and solution will already be available to me.

//The output would be the following.

At k=0  //This would be a randomly assigned number.

states = [[5,6],[7,9,8]]; state_out=[[1,2,3,4]]

solution=[[6,5], [7,9,8]]; solution_out=[[2,4,3,1]]

and so on until the states and solution become empty. When they become empty, I want all the values of the state_out and solution_out to be shifted to states and solution respectively maintaining the order the arrays have in state_out and solution_out.

`timescale 1ns / 1ps

module rubiks_states_solver(
input wire clk,
output reg [3:0][0:3] state_out,
output reg [3:0][0:3] solution_out
);

reg [3:0] k = 4'b0011;
reg [3:0] i;

reg [16:0] states[0:3][0:3];
reg [16:0] solution[0:3][0:3];
reg [16:0] state_out_mem[0:3][0:3];
reg [16:0] solution_out_mem[0:3][0:3];

initial begin
    // Initialize states and solution arrays
    states[0][0]=8'h61; states[0][1] = 8'h62; states[0][2]=8'h63; states[0][3]=8'h63;
    states[1][0]=8'h61; states[1][1]=8'h65; states[1][2]=8'h67;
    states[2][0] = 8'h6C; states[2][1] = 8'h67; states[2][2] = 8'h72; states[2][3] = 8'h74; 
    states[3][0] = 8'h6B; states[3][1] = 8'h68; states[3][2] = 8'h72;

    solution[0][0] = 8'h63; solution[0][1] = 8'h62; solution[0][2] = 8'h63; solution[0][3] = 8'h61; 
    solution[1][0] = 8'h67; solution[1][1] = 8'h61; solution[1][2] = 8'h65; solution[1][3]=8'h00; 
    solution[2][0] = 8'h6C; solution[2][1] = 8'h72; solution[2][2] = 8'h74; solution[2][3] = 8'h67;
    solution[3][0] = 8'h72; solution[3][1] = 8'h68; solution[3][2] = 8'h6B; solution[3][3]=8'h00;
end

always @ (posedge clk) begin
    for (i = 0; i < 4; i = i + 1) begin
        states[k][i] <= states[k][i] << 1;
        solution[k][i] <= solution[k][i] << 1;
    end
end

always @* begin
    for (i = 0; i < 4; i = i + 1) begin
        state_out_mem[k][i] = states[k][i];
        solution_out_mem[k][i] = solution[k][i];
    end
end
assign state_out = state_out_mem;
assign solution_out = solution_out_mem;
endmodule

at the (assign state_out = state_out_mem;) part, I am receiving syntax errors:

Error: cannot access memory "state_out_mem" directly
Error: cannot assign an unpacked type to a packed type.

same errors for the assign solution_out = solution_out_mem

Does anybody know how I can fix this issue?

Answer 1

Those are surprisingly helpful error messages.

The simulator is telling you that your assignment is too vague. You need to clarify what you mean to the simulator.

On the LHS, you have 16 bits. On the RHS you have 272 bits. You need to instruct the simulator which 16 of the 272 bits in state_out_mem you want to be assigned to state_out.

One approach you can take is to try to write the assignments out the "long way" first, explicitly using bit slices.