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I'm examining two design methodologies for IGBTs (Insulated Gate Bipolar Transistors) and have encountered a puzzling issue regarding the drain voltage in the nMOS part of an nMOS+PNP IGBT configuration.

In the first approach:

nMos+NPN

an nMOS is paired with an NPN transistor. This design demands an additional voltage source for the drain of the nMOS and introduces complexity in the control logic, given the inversion caused by the nMOS short-circuiting when the microcontroller outputs a high voltage.

In the second approach (nMos+PNP):

nMos+PNP

we pair an nMOS with a PNP transistor, which is preferred for its elimination of the extra voltage source and its straightforward control logic, allowing direct interfacing with the microcontroller.

My confusion arises with the second method concerning the drain voltage of the nMOS, which is equal to the base voltage of the PNP transistor. nMOS transistors typically do not handle high voltages well, but in this configuration, they seem to be subjected to high drain voltage. The base-emitter forward voltage drop (V_BE) of the PNP is traditionally about 0.7V, which is negligible in high-voltage scenarios. How, then, does the nMOS in this arrangement cope with the potentially high drain voltage without succumbing to the issues that high voltages usually present for nMOS devices?

I searched for PNP BJT Emitter-Base Voltage, not high enough to drop the Emitter voltage to a low level.

Scheme Source:

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  • \$\begingroup\$ "nMOS transistors typically do not handle high voltages well" -- Do they? Can you explain this claim, perhaps find a reference to support it? \$\endgroup\$
    – Tim Williams
    Commented Mar 15 at 19:39
  • \$\begingroup\$ @TimWilliams, The limitations of nMOS devices in high-voltage are outlined in the ref video, which mentions that MOSFETs excel in standard switching, their high-voltage tolerance is relatively poor, a challenge commonly addressed by BJTs. Additionally, from this link, I learned MOSFETs are rated for up to 1500V. However, this rating is insufficient for electric train/vehicle that can easily go beyond 2000V. \$\endgroup\$
    – Qiu Junpeng
    Commented Mar 16 at 6:50

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The IGBT is indeed constructed as as per the bottom diagram on your question. The NMOS transistor does indeed block the full voltage that is across the IGBT output terminals. A simple equivalent circuit model of an IGBT is pasted below, note the extra NPN BJT not shown in your question:

enter image description here

Ref:
https://www.nevsemi.com/blog/igbt-structure

The IGBT was first called "conductivity modulated field -effect transistor", or "COMFET". That name may give you a clue regarding how it was first constructed. One of the first patents referencing a COMFET was dated back in 1983, US4689647A.

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  • \$\begingroup\$ Thanks! The diagram left few questions: 1. without the NPN, can this diagram sill work correctly (theoretically)? 2. is Rd used to reduce the volt at D side of nMos? 3. if this IGBT is used to drive a motor, where to put the motor? Somewhere near R_by? \$\endgroup\$
    – Qiu Junpeng
    Commented Mar 21 at 2:45
  • \$\begingroup\$ 1. "work correctly": depends what you are trying to do. If you are trying to accurately model a real-world IGBT, then you need to include the NPN. I suggest downloading the spice model from the manufacturer of the IGBT. 2. Where to connect the motor: again, that depends on your circuit and what you are trying to achieve. This is beyond the scope of the original question, suggest you ask a new question and include the schematic showing how this IGBT is being used to drive a motor. \$\endgroup\$
    – Fabio Barone
    Commented Mar 21 at 3:59

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