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I have a design where an NXP i.MX8M nano CPU has a KSZ8081RNAIA Ethernet Phy connected. During prototype testing, we found now that the supply voltage rise time provided by the CPU PMIC (NXP PCA9450B) does not meet the requirements as stated in the KSZ8081 datasheet. KSZ8081 requires a rise time of min. 300µs (10%-90%) on VDDA_3.3 as well as on VDDIO (which is 1.8V in our case). The PMIC has a fixed output voltage slew rate of 12.5mV/µs, leading to a rise time of 210µs (10%-90%) on 3.3V, and 110µs (10%-90%) on 1.8V, respectively, which is lower than the minimum requirement in the KSZ8081 datasheet.

Since we cannot change the rise behaviorviour provided by the PMIC, will we have to expect troubles at KSZ8081? Or will these rise time values still allow safe operation?

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  • \$\begingroup\$ If the data sheet does not say, ask manufacturer for support. Have you tried that already? It would be a coincidence that someone here would know something about the internals of how that specific chip would behave if supply rise time is faster than specified. \$\endgroup\$
    – Justme
    Commented Mar 19, 2023 at 12:10
  • \$\begingroup\$ Generally, if a manufacturer is explicit regarding a spec, it’s wise to obey it. Some L and C might allow you to comply - run a simulation to see. Maybe you might require a separate reg? \$\endgroup\$
    – Kartman
    Commented Mar 19, 2023 at 13:02
  • \$\begingroup\$ @Justme thank you for the clarification. I did not ask the manufacturer for support yet. Just thought this might be a general question that might be applicable to other ICs too as this is a power supply question. \$\endgroup\$
    – Freshman
    Commented Mar 19, 2023 at 14:06
  • \$\begingroup\$ @Kartman, thank you for your suggestion \$\endgroup\$
    – Freshman
    Commented Mar 19, 2023 at 14:07
  • \$\begingroup\$ You can use a FET switch to delay the turn on of the KSZ8081 until the power source is fully on. \$\endgroup\$
    – RussellH
    Commented Mar 20, 2023 at 0:04

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