How to monitor the HWDATA and HRDATA in AHB-LITE on the all clock?

Question

I'm trying to monitor the HRDATA and HWDATA on the AHB-Lite bus transfer.

The monitor message should only appear when a command(Read/ Write) is issued. because this monitor connected to Scoreboard, I need the monitor signals when they are issued in Scoreboard.

So I implement the Benjamin's idea in to the Monitor by using HTRANS.

 if(ahb_if.HWRITE==1 && ahb_if.HTRANS==NONSEQ) begin
        rsp.HWDATA = ahb_if.HWDATA;
        `uvm_info(get_type_name(),$sformatf("Rcvd wr data=0x%h", ahb_if.HWDATA),UVM_LOW)
      end
      if(ahb_if.HWRITE==0 && ahb_if.HTRANS==NONSEQ) begin
        rsp.HRDATA = ahb_if.HRDATA;
        `uvm_info(get_type_name(),$sformatf("Rcvd rd data=0x%h", ahb_if.HRDATA),UVM_LOW)
      end 

then I got the message as per the condition after Update 1: Proposed Fixed output

But Problem is that the write and received data start with'xxxx. How can I get the one cycle delayed HRDATA and HWDATA from the monitor?

This is the snippet of monitor

    virtual task run_phase(uvm_phase phase);
    fork  
      do_ahb_trans();
      do_ahb_trans();
    join
    endtask 

  
  // capture ahb transaction pipeline
  task do_ahb_trans();
    ahb_seq_item rsp;
 
    forever begin
      addr_key.get(); // lock addr pipeline
      // wait for new trans addr accepted
      do wait_cycle(); while(ahb_if.HREADY !=1 );
      //`uvm_info(get_type_name(),$sformatf("Rcvd addr=0x%h", ahb_if.HADDR),UVM_LOW)
      
      rsp = ahb_seq_item::type_id::create("mon_item");

      // send cmds to cmd_fifo only in active slave mode for driving responses
      addr_key.put(); // unlock addr pipeline

      rsp.busy = new[1];
      wait_ready(rsp.busy[0]);  // wait for data accepted

      if(ahb_if.HWRITE==1 && ahb_if.HTRANS==NONSEQ) begin
        rsp.HWDATA = ahb_if.HWDATA;
        `uvm_info(get_type_name(),$sformatf("Rcvd wr data=0x%h", ahb_if.HWDATA),UVM_LOW)
      end
      if(ahb_if.HWRITE==0 && ahb_if.HTRANS==NONSEQ) begin

        rsp.HRDATA = ahb_if.HRDATA;
        `uvm_info(get_type_name(),$sformatf("Rcvd rd data=0x%h", ahb_if.HRDATA),UVM_LOW)
      end 
      mon_ap.write(rsp);
    end 
  endtask 

  task wait_cycle;
    @(posedge ahb_if.HCLK);
  endtask // wait_cycle

  
  // wait for hready
  task wait_ready(output int busy);
    busy = 0;
    // wait for data accepted
    do begin
      wait_cycle();
      busy++;
    end while(!ahb_if.HREADY);
  endtask // wait_ready

Answer 1

Per the AMBA3 AHB-Lite Spec a transaction occurs on any clock cycle where HSELx == 1'b1, HREADY == 1'b1, and the previous clock cycle HTRANS inside {NONSEQ, SEQ}. So even if the master isn't deliberately requesting a transaction the slave should respond as though it is a legitimate transaction unless HTRANS == IDLE.

The HWRITE signal simply determines which direction the data is being transferred.

As far as HREADY and HRESPS being fixed, I would hazard a guess that, if this is a simple register bank, the AHB slave can guarantee timely and valid responses within one clock cycle. I have seen these implementation tactics used by several automated register bank creation tools.

Update 1: Proposed Fix

I have update the condition in the initial wait cycle while loop. It appears that though you were checking the state of the HTRANS later, this was only after having committed to an AHB sequence item. By moving the checks for a valid transaction up higher we can avoid creating these invalid transactions.

forever begin
      addr_key.get(); // lock addr pipeline
      // wait for new trans addr accepted
      do
            wait_cycle();
      // EDITS IN THIS WHILE STATEMENT
      while(ahb_if.HREADY != 1 || 
            ahb_if.HSEL != 1   ||
            !(ahb_if.HTRANS inside {NONSEQ, SEQ}));

      
      rsp = ahb_seq_item::type_id::create("mon_item");

      addr_key.put(); // unlock addr pipeline

      rsp.busy = new[1];
      wait_ready(rsp.busy[0]);  // wait for data accepted

      if(ahb_if.HWRITE==1 && ahb_if.HTRANS==NONSEQ) begin
        rsp.HWDATA = ahb_if.HWDATA;
        `uvm_info(get_type_name(),$sformatf("Rcvd wr data=0x%h", ahb_if.HWDATA),UVM_LOW)
      end
      if(ahb_if.HWRITE==0 && ahb_if.HTRANS==NONSEQ) begin

        rsp.HRDATA = ahb_if.HRDATA;
        `uvm_info(get_type_name(),$sformatf("Rcvd rd data=0x%h", ahb_if.HRDATA),UVM_LOW)
      end // if
    
      mon_ap.write(rsp);
    end // forever