Output with programmable rise time

Question

I am tinkering with a device to generate pulses for a measurement setup. No need to buy it: Just wondering how one would implement it.

Idea:

Device generates a square-wave (Vpp and DC-offset) output between V- and V+ with frequency f, duty-cycle d, and rise = fall times of t.

Requirements:

Vout: -5V <= V- and V+ <= +5V, adjustable via DAC (Vpp and offset)

Frequency: 10 Hz<->1 MHz with 1 Hz resolution and low jitter (Maybe via uC timer?)

Duty-cycle between 10 and 90% (maybe via uC timer?)

tRise/tFall adjustable between 1 ns and 10 ms (Yes, 10 ms for the low frequencies). The rise/fall portion of the square wave should be fairly linear.

The operations are somewhat simple: Set offset and Vpp, set f/d/tRise/tFall and generate a pulse-train for example. Or a continuous signal if you like.

My ideas:

I get my head around the output-stage: Feed the "finished" (correct wave form, normalized amplitude and DC offset) into a analog-stage which adds DC offset and scaling based on DAC outputs. Feed it into 50 Ω BNC. So far so good.

I also can get my head around how to generate the variable signal (control frequency and duty cycle) via an uC timer for example.

What I can not get: How to make the rise/fall times controllable in some way? I mean, you could oversample the signal with a DAC pretty hard -> let's say 100 MSamples would allow to "approximate the ramp" in 100 steps. But there have to be different ways to do this, which I can't come up with.

Question:

How could one implement this without oversampling/approximating the waveform with a really fast DAC?

Are there some op-amps out there which give you configurable (e.g. via analog-input) slew-rates? Or are there logic gates which can do this? Are there any parts (especially over the entire range 1 ns<->10 ms)?

I mean you could also use a good ARB and build "parametric-waveforms" of some sort, but this goes down the "sample a DAC really fast" road.

Edit 1:

Based on user4474's input I came up with this idea:

^{simulate this circuit – Schematic created using CircuitLab}

This should give a output voltage which swings between V-<->V+ with "controllable" ramp rates based on the DAC bias voltages. The actual signal is generated via PWM and can be fed into the switches connecting the DAC voltages to the circuit.

Then, based on four switches, the desired signal is derived and can bee feed into the scale and offset stage.

Edit 2:

Based on Kuba hasn't forgotten Monica answer i drew up a shematic.

A variable amount of current is forced thorugh a integration capacitor C_i. Therefore a speific voltage is across the voltage based on the time and the amount of current used. The Ramp can therefore be controlled by controlling the current thorugh the cap. This voltage is buffered and scaled / Dc-offset and pushed into the output.

To limit transient effects when switching current sources, they pump their current into an op-amp at the same voltage as the integrator cap if not in use. For switching one could use Make-Before-Break Analog switches. The voltage accross the integrator is limited to a given threshold with two op-amps (positive and negative clamp).

The raw PWM signal can be used to manipulate the current soure switches, while the "ramp-rate" can be controlled by a I(u) source of some sort (DAC with Op-Amp).

Rising/Falling Edges can be achieved by sourcing/sinking positive/negative current "into" the C respectivly.

Answer 1

Fast pulse generators with controllable slew rates typically use current sources, current switches, and clamps.

The diagram below illustrates the key parts of one design for such a generator:

^{simulate this circuit – Schematic created using CircuitLab}

The "central" component is the integrating capacitor C1. Rising- and falling ramps are generated by connecting one of two current sources to the capacitor. High and low output levels are established by clamps that act as ideal diodes.

When the current sources are not used to charge or discharge the integrator, they are "parked", or bootstrapped, to the integrator potential. This minimizes the transients, as the current source output voltages don't need to slew when they transfer from the parking node to capacitor node.

In practical implementations, the high-current sources used for fast slew rate range and low-current sources used for long ramps usually end up separate, since their circuitry has to be optimized for speed and precision, respectively.

The current-source switches need relatively low charge injection - matched bipolar transistor pairs usually excel at this task. The parking/bootstrap buffer needs to be a fast voltage follower, with offset trimmed to zero. The output buffer can have selectable gain, per desired output voltage range.

There are various designs possible for the clamps, with their own trade-offs. One possible implementation uses a fast comparator to "shut down" the current source (redirect it to the parking/bootstrap node).

^{simulate this circuit}

The idealized output voltage and switch control waveforms are shown below.

Old school 1-2ns comparators can be made with an avalanche threshold detector with a pulse output using e.g. 2N2904, appropriately biased, and a pulse stretcher (see e.g. Linear Technology AN72, page 34).

There are modern comparators that propagate on the order of 1ns, and those would be easier to apply here.

We could start implementing this idea with more realistic current switches:

^{simulate this circuit}

The performance is similar to our initial model:

Now we can implement the bootstrap buffer:

^{simulate this circuit}

Q5-Q8 cascode the current sources and bootstrap the collectors to a roughly fixed potential.

Since the current sources are double-cascoded, the emitter potentials of the current switches are quite stable, and an unsophisticated low-frequency op-amp based current source can be used.

^{simulate this circuit}

The performance is still reasonable for how simple the circuit is so far:

Answer 2

You can create a controlled ramp rate by feeding an integrator circuit with a DAC output.

I would suggest segmenting this design into two generators. One that goes from like 10Hz to 10kHz, and another that goes from 10kHz to 10MHz. That would make each section only need 1000:1 range on the timing (which can be done with 10 bits of resolution). You can then use a telecom relay to pick which output you want.

^{simulate this circuit – Schematic created using CircuitLab}

The circuit shown will ramp towards +5V or -5V with a variable rate depending on the DAC output. I relaxed the 1ns rise time to 10ns otherwise there would likely be zero chance of finding an op amp that could meet the timing requirements.

The capacitors should be NP0 type for high stability and good frequency characteristics.

The precise slew rate in V/s on the op-amp output is...

$$SLEW = \frac{-DAC_{VOUT}}{R*C}$$

For the fast side its...

$$SLEW = -DAC_{VOUT}*212MV/s$$

For the slow side its...

$$SLEW = -DAC_{VOUT}*200kV/s$$

The slew out signal should then feed into your gain and offset circuit. You could also put the gain and offset before the relay so you could use different parts for the high and low frequency sides.