I've often heard a couple of "good practices" for TQFP/QFN ICs fanout:
Do not route corner pins at 90°, instead the track must come straight to the pin:
Do not short the signals directly at the pad, but rather extend the track and do the junction outside of the footprint:
I imagine it doesn't really make a difference from a signal integrity perspective, but rather help/simplify AOI. Is there an official IPC/JEDEC guideline for those, or are they just "good practices"?