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I am reading about Memory Addressing and have found one notation of an address: N x N memory ( row x column addressing). I read these posts 1, 2, 3, but they didnt help me to figure out my question.

What is row-column addressing? what is a difference between a standard and this type of addressing?

PS It seems for you it is a stupid question, but for me as a beginner it is important to understand it

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  • \$\begingroup\$ Can you describe the problem any better? I mean, do you mean how memory chips internally access the memory cells regardless of what kind of external interface the chip provides, or what kind of externan interface the memory chip provides for accessing the memory? Is this about some certain memory type, such as DRAM, SRAM, Flash, etc? \$\endgroup\$
    – Justme
    Commented Aug 12, 2021 at 7:48
  • \$\begingroup\$ Are you familiar with the process of decoding M address bits into 2^M lines? \$\endgroup\$
    – AJN
    Commented Aug 12, 2021 at 8:14
  • \$\begingroup\$ @Justme I was reading about an addressing in e Zynq-7000 DDR and Row-column addressing scheme is appeared in the topic "address mapping" ( for ex here) \$\endgroup\$
    – Anna Koroleva
    Commented Aug 12, 2021 at 9:00
  • \$\begingroup\$ @AJN address decoding? Oh..i have never heard about it \$\endgroup\$
    – Anna Koroleva
    Commented Aug 12, 2021 at 9:01
  • \$\begingroup\$ I think the two first references are talking about something else: byte vs word addressing which actually has nothing to do with row-column addressing. The x8, x16 and x32 are how many bits are stored in a single column in those questions. A simple example would be an 8-bit computer with lets say 32K x 8 RAM: it would have 8 chips (one for each databit) of 128 rows and 256 columns. \$\endgroup\$
    – Oskar Skog
    Commented Aug 12, 2021 at 11:02

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So the context is about DDR memory, which is a type of DRAM memory.

DRAM memories typically contain a lot of memory which is internally organized into a 2D array with rows and columns anyway, so to conserve the amount of address pins, there is only a single set of address pins, that are uses for sending both the row and column addresses one after another.

So let's say it's the 1970s and you have a 64 kilobit memory chip. It would require 16 address pins just for the address pins alone. So if the 16 address bits are sent in two phases, first the 8 bit row address and then the 8 bit column address, there is only need for 8 address pins. So the whole memory chip can now be packaged into a cheaper package with a total of 16 pins instead of more expensive 24 pin package.

And thus we still have dynamic memories with row and column addresses.

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    \$\begingroup\$ There is no point in separate row and column address pins -- the row needs to be loaded into the amplifiers first, then columns can be addressed, so the column address is needed way later than the row address, and if these were on separate pins, one set would be unused at any time. \$\endgroup\$
    – Simon Richter
    Commented Aug 12, 2021 at 9:26
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    \$\begingroup\$ @SimonRichter There is a point for separate pins if you consider the issue from the processor's point of view. The processor naturally produces all of the address bits at once, and it is inconvenient and slower to have to separate the bits according to the memory's organization and then manage providing the row and column sequentially. \$\endgroup\$
    – Elliot Alderson
    Commented Aug 12, 2021 at 11:00
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    \$\begingroup\$ @SimonRichter You are right that row is needed first and column later, but multiplexing the address bus is simply done because it is possible and more economical to do so. The 1024-bit Intel 1103 had a straight 10-bit address bus, so it required both row and column addresses at once, still only using 18 pin package. Some other chips may use multiplexed address and/or data buses too. \$\endgroup\$
    – Justme
    Commented Aug 12, 2021 at 11:13
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    \$\begingroup\$ @ElliotAlderson, access times to the active row are (much) shorter, so the memory controller will need to know the memory organization nonetheless, and reorder requests so accesses to the same row are consecutive, so there is already a state machine that tracks whether row address changes for the next access. The processor generates requests with a full address bus, but the external signals you see are the interface between the memory controller integrated into the CPU die, and the memory modules. \$\endgroup\$
    – Simon Richter
    Commented Aug 12, 2021 at 12:02
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    \$\begingroup\$ @SimonRichter I understand all of that. My point is that if DRAM had the same kind of pinout as SRAM we wouldn't need the integrated controller to talk to it. That would be one advantage to having all of the address pins brought out separately. So, you can say that there are many advantages to having row/column addressing you can't say that there are no advantages to having separate pins. My issue is with your wording of the statement. \$\endgroup\$
    – Elliot Alderson
    Commented Aug 12, 2021 at 13:39

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