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I have understood that via on pad is bad for automatic assembly processes, but can be fine for hand soldering, since it is easy to compensate for the solder that wicks into the via.

I am doing a small hobby project with a BGA FPGA on the component side. Dog bone pattern, no buried/blind vias. I can get the BGA pre-assembled, but not decoupling caps on the bottom side. Filled vias is not an option.

In order to avoid 0201 caps, I would need to put the bottom bypass caps over the dog bone vias. Is there any risk that hand soldering the bottom pads may cause solder to pop up under the BGA and cause a short? Or is there any other reason not to do this in these circumstances?

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  • \$\begingroup\$ What is the PCB thickness, and the via hole sizes you're referring to ? Is there solder mask on the BGA pads ? What is the BGA pitch ? \$\endgroup\$
    – citizen
    Commented Jan 28, 2021 at 14:19
  • \$\begingroup\$ There probably isn't enough solder in the solder balls to fill the via (assuming the entire solder ball doesn't get wicked, which would be odd) I assume when you say "hand solder" you mean hot plate or hot air? \$\endgroup\$
    – Ron Beyer
    Commented Jan 28, 2021 at 14:19
  • \$\begingroup\$ @RonBeyer The BGA will be pre-assembled and has no VIAs under the pads. He only wants to solder the decoupling caps on the other of the PCB by hand. \$\endgroup\$
    – jusaca
    Commented Jan 28, 2021 at 14:59
  • \$\begingroup\$ @citizen 1.6mm, 0.25mm via drills, LPI mask. 1mm pitch. There will be mask on the top, covering the vias. I have understood that there is no guarantee this will fully block the holes. But I trust that the BGA can be soldered correctly, as there is nothing unusual going on here. \$\endgroup\$
    – joro
    Commented Jan 28, 2021 at 15:03
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    \$\begingroup\$ "Small hobby project" and BGA should be mutually exclusive. Is there no QFP option? \$\endgroup\$
    – Lundin
    Commented Jan 28, 2021 at 15:10

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Yes, it can be done, but you may need to slightly enlarge your 0402 cap pads to ensure the hole in the middle doesn’t take up all of the exposed pad area.

However, I recommend a different approach. Depending on your requirements, you could try putting the caps on the same side of the board as the FPGA. This isn’t always ideal but it can be made to work for many applications, and can even be superior to caps on the back in some cases.

What you need to do is approximate the inductance between your FPGA’s power and ground pins with caps on either the front or back. If you can design your layout such that the inductance with caps on the front is not too much greater than with caps on the back, then your board will work unless your system is approaching the limits of SSO noise, etc.

But how do you estimate this inductance? Inductance in a circuit is proportional to the area enclosed by that circuit. In your application, the circuit is between the FPGA Vcc, cap Vcc, cap GND, and FPGA GND. Here is a visualization of the inductance estimation (courtesy EDN):

Inductance of bypass capacitor (courtesy EDN)

Do this estimation for the case where you have caps on the front and caps on the back. If you can minimize the area enclosed, then your system will likely work. Consider using additional closely-spaced power and ground planes to minimize the inductance. Indeed, if using very closely-spaced power and ground planes which are close to the component side of the board, it is possible to achieve lower inductance with caps on the front than on the back.

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