Remove/exclude exposed pad of QFN package from PCB layout

Question

I am doing a PCB layout with a Atmel/Microchip MCU ATSAML21E18B-MUT‎ which has QFN-32 package 5x5 mm. This board can have a maximum of 20x40 mm and I am having problems with space because the circuit is not very little and also there is an NFC antenna on-board that occupies 14x14 mm on both sides.

The drawing of "32 pin QFN" is on page 1123. The datasheet does not mention if this pad should or not be connected to GND or other signal.

Check my current drawing of QFN-32 package on the current layout below, there is a 2.8x2.8 mm square pad in the center, also known as an exposed pad. I want to delete it... in order I can route tracks and vias below the QFN package. Doing this I would finish the layout easily.

And, when assembling the boards, I want to place an electrical insulation material between the IC package and the board, to guarantee there will be no short-circuit between the center pad of the QFN-32 package and a via or track, for example, if the solder mask doesn't guarantee it.

Then, in this case, can I securely remove the center pad of the QFN-32 from the PCB layout?

• OBS1: It is a double-side board, there is no possibility to go multilayer.
• OBS2: The IC does not heat.

The package:

Answer 1

My conclusion upfront: It's not worth considering going your route, the potential downsides outweigh the fact that you might get a more compact layout.

Generally, you'd have to triple-check that your device doesn't run too hot with the thermal pad unconnected. So, you'd have to use the datasheet (thermal resistances) and a power model of your IC to estimate how much electrical power gets converted to thermal energy in your actual application, and estimate whether the die-to-top-of-package || die-to-contacts thermal resistance is low enough for the device to stay cold enough. Then you'd have something that probably works.

I'd have a slightly queasy feeling about that. Microchip added that thermal pad to the package for a reason.

Also, let's talk layout here:

With your trace width, you can only route 1 top-layer trace between the pads on the corners; so, no need for more clearance on the top layer than you already have. Bottom layer: you have a lot more freedom. You'd want to connect a large ground plane to the top layer thermal land through a couple of vias, but nothing's forcing you to make that cover the whole bottom of the IC package.

Anyway, what you've drawn as bottom layout doesn't look OK to me. Decoupling caps don't help much if the ground current path is worse than the Vcc path! So, your layout looks questionable on more than the thermal side of things.

So, re-layout the whole thing, starting with the attempt to put as little as possible on the bottom layer – and if possible at all, have one large, uncut ground plane. Yes, that will bump all our bottom-side components to the top side. But please believe me, during assembly (or, when paying someone to assemble), you'll be happy when you've eradicated the need to solder SMD on two sides.

One more thing: make sure your top-side capacitors are out of the keepout zones of the QFN package. What you've placed looks unncessarily hard to solder.

Generally: If this is one of the first designs you do, start with a board with four times the space you'd love to use in the end, and lay it out completely, following best-practice rules of keeping the ground plane clean, arranging passives in groups that are easy to assemble/solder, including enough test points, having really enough decoupling caps, and so on. If your finished design then really looks like you can shrink it down in both dimensions by one half, do that. Don't start with "I need to squeeze this down to the smallest possible area"; that almost always goes wrong (believe me, that's how I lost my first couple of boards).