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When designing a QFN footprint, I've read from (reputation limited, only 2) sources...

...that the QFN should sit approximately 50-75um (2-3 mil) high off the board for reliable solder joints. I assume that this "standoff" height is created by the solder joints themselves.

So far I have gathered:

  1. Use ENIG or OSP finish. This provides the most flat surface (necessary for applying the stencil, paste and placing the package).
  2. For the center pad (a.k.a. exposed pad, EP, thermal pad), use a SMD (solder mask defined) pad.
  3. For outside (a.k.a perimeter) pads, use non-SMD pads. NSMD pads will result in a pad that is most accurate to your design because copper etching has a tighter tolerance than solder mask.
  4. Extend perimeter pads towards center of package 0.05mm and away from package ~0.2-0.6mm. This provides a more reliable solder joint and potentially allows for easy rework since the pad will extend outside the package.
  5. For QFNs at a pitch of 0.5mm and below, keep PCB footprint pad width equal to package pad width. For 0.65mm and above.
  6. For QFNs at a pitch of 0.5mm and above, you can define the solder mask between pads. For QFNs at a pitch of 0.4mm and below, define an area that keeps mask out for each row of pads on the QFN.

There are many variables here.
The answer I am looking for would define a stencil thickness and aperture opening relative to pad size and pitch. Does the center pad or do the perimeter pads have the most effect on standoff height?

How important is the standoff height?
Are the datasheets simply warning us not to float the part with too much solder in the middle?

Past experiences in production environments as well as prototype (DIY, applying stencil and paste by hand) would be incredible.

What design parameters influence the "standoff" (or solder joint) height?

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    \$\begingroup\$ Anton, welcome to EE.SE. If you have read something somewhere, then please provide a link or a reference for the rest of us. That would provide better context for the question, and answers will be more accurate. \$\endgroup\$
    – Nick Alexeev
    Commented Sep 5, 2015 at 1:56
  • \$\begingroup\$ Thanks Nick for your advice and welcome. I've updated my original question. Let me know if it's too opinionated or too "discussion"-y. [Isn't stack exchange only for asking specific questions that have one answer?] \$\endgroup\$
    – Anton
    Commented Sep 10, 2015 at 0:26

3 Answers 3

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That's going to be determined by the thickness of the stencil and the opening size, or if no stencil the thickness of the solder paste printed on the board. I believe it's a warning that too much paste will float the part and then you might not get good joints all around, or maybe the part might be uneven etc.

The only way you could affect it is if you are defining the paste layer yourself then you define the opening and put an assembly note in about stencil thickness.

But really I would say you should leave this to your assembly house to adjust correctly for their process when they order the stencils. They have to look at all the parts in the board and find a method that will work for all of them, it's part of the magic of being a good assembly house.

Here by the way is a link that talks about it more. Note that their guideline if a 2-3 mil standoff is "after assembly". Not a you should have a 2-3 mil standoff before assembly...

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  • \$\begingroup\$ I accepted this answer because it's the best answer in general. The link from Screaming Circuits is good. I have actually used them as an assembly house before. \$\endgroup\$
    – Anton
    Commented Sep 10, 2015 at 18:29
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Your assumption is a little wrong. The solder joints themselves are created across the standoff gap between solder pad and the lead protrusion on the QFN part.

The things that contribute to the lead standoff would be:

1) Use a thin plating on the pads of your board such as immersion gold as opposed to a thick er plating such as hot air leveled solder.

2) The thickness of the solder mask over the copper will tend to elevate the QFN package up above the copper level by a small level.

3) Some boards I have seen also place a patch silkscreen of white screening ink under the base of QFN which will elevate the part a little more above the copper plane.

4) It is possible that some QFN type packages may be designed to have the base of the package protrude below the lead plane by a small amount.

This whole scheme does not work when the QFN part is one of the type with a integrated heat spreader on the bottom of the package that is meant to be soldered to a GND pad.

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  • \$\begingroup\$ The plating type may influence how successful the assembly process is, but not overall standoff height of the package relative to the pads... (all pads are going have the same height from plating). That being said, ENIG is the way to go because it is much flatter vs HASL. When you are laying down your stencil, paste, and placing parts, you want everything to be as flat as possible. \$\endgroup\$
    – Anton
    Commented Sep 10, 2015 at 18:09
  • \$\begingroup\$ I accepted other answers because I believe the answer is mostly related to the stencil, solder paste and thermal pad footprint design (solid vs hatched). \$\endgroup\$
    – Anton
    Commented Sep 10, 2015 at 18:17
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The thickness of the solder beneath the exposed pad determines the final stand-off height. The aperture for the solder stencil is usually about 50% of the pad size, as this ensures the device does not simply sit on top of the solder and the contacts around the edge may or may not connect (or worse, the device tombstones). By having a reduced aperture, the solder spreads at reflow and literally pulls the device down into the solder at the edge contacts.

I usually specify a 5 thou solder stencil and the spreading solder under the exposed pad yields about 3 thou finished height.

Excellent article about defect free QFN soldering at SMTNet

HTH

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