I would just set the PWM's duty-cycle to 100% in that case, which is equal to a logic 1.
This way, you never actually have to stop the timer and only need to modify the timer cannel's Capture Compare Register (CCR).
For a 100% duty cycle, you need the value of the CCR register to match (or exceed) the value of the timer's Auto Reload Register (ARR).
Both, the CCR and ARR are preconfigurable in CubeMX but you can read and write them by HAL-Library Macros.
As an example:
uint32_t arr = __HAL_TIM_GET_AUTORELOAD(&htim1); //Read Auto Reload Register Value of TIM1
uint32_t crr = __HAL_TIM_GET_COMPARE(&htim1, TIM_CHANNEL_3); // Read Capture Compare Register of TIM1C3. Save it to turn back to original duty-cycle.
__HAL_TIM_SET_COMPARE(&htim1, TIM_CHANNEL_3, arr); // Set TIM1C3 CRR to TIM1 ARR for 100% pwm output. Equals logic 1.
Things might be a bit different depending on the configured PWM-Mode and Output Polarity. In some cases you must set your CRR to 0 to get a logic 1.