Can Class D output capacitors be placed towards both rails?

Question

Please consider the simplified Class D output stage below. Depending on the half-bridge duty cycle, different output voltages (within the power supply range) can be applied to the load.

^{simulate this circuit – Schematic created using CircuitLab}

The output filter is usually an LC filter like shown in the schematic. For all schematics that I have seen so far, the output capacitance is placed only in the position of C1, i.e. to the negative power rail. Now, for an application like a synchronous buck, that goes from 12 V to ~1 V that might be sensible because less bias will be present across C1 than across C2.

But when this topology is used to generate varying output voltages, both close to the positive or negative power rails (like e.g. in a Class D audio power stage), the DC bias of the output capacitors can change their effective value rather strongly for the case of usual X5R ceramics for example.

So I was wondering if one could distribute the output capacitance between C1 and C2 (i.e. to both power rails) to somewhat mitigate the effects of the DC bias on the total capacitance. Spice shows that the inductor ripple current nicely splits between both capacitors, so they are effectively in parallel for the ripple current. Is this a good practise to implement output capacitors ? It somehow doesn't look right to me.

Answer 1

Yes, and this might be better in certain technical aspects (startup transient, nonlinear capacitors), but less so in practical aspects such as EMI where the negative rail may be the reference plane. (I think it's more likely such a class-D amp has a common ground rail, which makes more sense in this regard.)

But EMI may be a small issue, as a subsequent LC filter could be applied against the reference plane, easily addressing RFI issues at least. (A filter stage at EMI frequencies probably affects the overall filter design, so can't just be tacked on, just something to keep in mind.)

Answer 2

Assuming you'll have a PI filter in which the L has a non-zero DC resistance, with the split cap configuration there's going to be large peak currents (larger than the inductor current's peak) flowing through the caps during the rising and the falling of the bridge voltage ^{(assuming the load is Vpow- referenced)}. The peak values depend on the rate of change (rising and falling). Since the difference of these currents is be equal to the inductor current, there won't be any peaks visible at the load side. However, depending on their values, these peaks may lead to a temperature rise for the caps which may result in extra capacitance decrease. And not to mention possible EMI issues. Slowing down the rate of change by adding some capacitance across the switches might be a solution but it's not always under the designer's control or it's not always possible or easy.

With single cap arrangement none of the issues mentioned above will be present.

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The advantage is, as you mentioned, relatively higher effective capacitance. The DC bias of each cap will dynamically change so while one cap has lower capacitance the other will have higher. But the difference may not be that noticeable.

Here's an example:

Assume the supply voltage is 12V and two 1812-case 4.7u/25V (having the following graphs) are used for C1 and C2:

If the duty cycle is 25%: For split cap arrangement, the voltages across the C1 and C2 will be 3V and 9V, respectively. At 3V C1 will be ~4.7u, and at 9V C2 will be 4.4u, so the effective capacitance will be 9.1u. If these caps were in parallel across the output, both of them would see 3V and the effective capacitance would be 4.7u x 2 = 9.4u.

If the duty cycle is 50%: Split cap and the other would bring equal effective capacitance.

If the duty cycle is 75%: Split cap arrangement would bring 9.1u while the other arrangement would bring 8.8u.

So the difference doesn't seem to be noticeable. However, in applications where the capacitor's voltage could be close to their rated voltages then the difference would be more noticeable. See what would the results be for 24V supply voltage.

To me, the benefit doesn't seem to be worth to make the layout a bit more complex.

Answer 3

I have done this with caps in 1995 .This was before Spice simulation being common .My application had 3 470microfarad old school phillips 037 35VDC eltec caps .Input voltage was 24 and 12 VDC out. Hence duty cycle was about 50% . No reliability issues or emc problems .Now younger engineers have simulated this with no suprises.