Half-Bridge Switching Transition

Question

Please see this video (from 6:43:40): https://youtu.be/FXbciGTDQuY?t=24223

They are explaining switching transitions in a synchronous buck converter. He says that when the high-side FET is on, the switching node (Vs) will rise. At this point, the low side FET Vgs is 0V. So, there will be a current flow into the parasitic Cgd cap of the low side FET.

He says that this current cannot flow to the gate driver voltage source because there is 0V on both sides of the gate driver Rth resistance. I don't understand this. My understanding is that : There WAS 0V at the gate of the low-side FET, however due to the current from Cgd, some current will flow to Rth and cause it to rise.

Can someone explain in more detail why no current flows to Rth?

Answer 1

He's describing the first instant of the transient, yes. As Vgs begins to rise, I(Rth) will also rise.

Note that Cdg + Cgs act as a capacitive divider, so the Thevenin theorem can be applied to them as well: as Vds rises, Vgs(thev) rises as a fraction of it determined by the divider ratio, with a source impedance of Cgd || Cgs. Rth then discharges this capacitance. The result is a differentiator, a blip in voltage that goes up momentarily, then subsides.

I haven't watched the entire section; perhaps he gets to this in time.

It seems he's explaining it one component at a time, so indeed, the current from Cdg has to go somewhere, and initially it goes into Cgs, then then into Rth || Cgs, as the voltage changes as I just described.

Answer 2

There is a negative feedback effect with Miller Capacitance from Drain to Gate.

Although that is a small ratio the gain with an inductive current going off gets damped by the base resistor which serves to match the gate resistance in high current transitions. Trace reactance and load can play a role in noisy transitions.