The answer reads in the picture you quoted.
CBST is charged from CDRV.
Each time the FET is turned on, a small charge is drawn from CBST to charge the FET gate, and each time the FET is turned off, the CBST capacitor is recharged from CDRV capacitor via the DBST diode.
Since charging the CBST capacitor takes short high current pulses, the CDRV capacitor is the nearest bypass capacitor, a local storage from where large current surges are quickly available, as the short wires to it have very little inductance and resistance.
If there is no CDRV capacitor, there would be longer wires to power supply, or to nearest capacitor elsewhere. This means more resistance, so less current is available to charge the CBST so it does not happen so quickly, and due to resistance, there is a drop in the supply voltage at the chip when it draws a pulse of current. Longer wires mean also more inductance, so the current rises slower to the maximum value set by wire resistance. Also the larger inductance causes larger voltage drop during a pulse of current.
So basically, the CDRV is called a bypass capacitor, page 35 of the document you linked explains approximately same thing than the above writing, and page 16 has a lengthy explanation how to calculate the required capacitance for CDRV.