How to use 1PPS to Synchronize ESP32 Clocks and Peripherals

Question

I've read a few posts (example) about what the 1PPS signal is and how it can be used at a high-level, but I'm still not sure how to actually implement it on a PCB schematic to sync up with my microcontroller (ESP32). Do I just connect the 1PPS to a GPIO on the ESP32 and configure the rest in software? What would that look like?

For reference, here's my schematic showing just the MCU, external flash, and my crystal (configured based on the ESP32 Hardware Design Guidelines). You'll notice there's four different clock frequencies. How can I calibrate all of them based on the 1PPS? What are the hardware steps and subsequent firmware steps?

Answer 1

I'm not sure what it is exactly that you want to "calibrate", but I worked on a very similar project several years ago, and came up with a scheme that worked fairly well for us.

In our case, we had a GPS receiver providing position fixes and a 1 PPS signal to our processor, and we needed to be able to precisely interpolate 5 ms intervals (200 Hz) from the 1 PPS so that we could accurately control the sampling of the IMU. (Additional background material here.) However, we had no direct control over the CPU clock, which also drove its hardware timers. Therefore, I invented a kind of "software PLL" to fill the gap.

The basic idea is that we set up a hardware timer (call it T1) to produce the 5 ms interrupts we needed. Suppose the processor clock is nominally 50 MHz. Therefore, the T1 period is nominally (but not exactly) 250000 CPU clocks. We keep track of the passage of time through a combination of reading the hardware timer and counting the number of T1 interrupts that have occurred.

The 1 PPS signal is connected to a second timer (T2) that simply "captures" its value in a register and also triggers an interrupt, at which time we also take a snapshot of T1's value. T2 gives us the exact number of CPU clocks between 1 PPS edges, which is an exact measure of its actual frequency. The period of T1 needs to be 1/200 of this value, which is not always going to be an integer.

Therefore, we dither the T1 period between two adjacent values, keeping track of the accumulated error and updating it on every interrupt. We can also control the "phase" of the T1 interrupts relative to the T2 interrupt in order to create an offset that accounts for any unavoidable latency in the processing.

This is a very general description of what we did. Let me know if anything is not clear.

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However, from your comment about what you're doing, it sounds like you don't need anywhere close to this level of precision (i.e., a few µs). Just read the timestamps in the GPS messages.

Answer 2

First state your specs !!

This may mean your question is irrelevant.

If you have a GPS, you can always get the message of real time.

So do you want to null frequency error or get accurate time? Then what tolerances for either?

If you only need an accurate clock frequency, you can buy these cheaply instead of using a crystal. (X) It will be temperature compensated and thus called a TCXO crystal oscillator chip and costs ~>$1, depending on Qty and [ppb or ppm] frequency error and temp. range.

Other corrections

SER4045CT-ND is Digikey's part number for a 10pF 40MHz Xtal from Epson

Therefore change your load caps from 100pF to 15~20pF to increase to nominal f C1+C2+ Stray+C input= load pF to include stray input.

Same for 38kHz Xtal is 9pF, therefore, 18pF on out and 15~18pf on input.

If you want an accurate frequency this is done with time interval counts best with high resolution as the counts must exceed your desired error in ppm. Again the time interval of this error averaging must be defined in your SPEC.

If the frequency error is less than your resolution, you cannot read any error. So to force this without having to use 32-bit counters, you can inject a sine wave lookup table of offsets to exceed your resolution and accumulate your error. Or it could be a binary offset of phase incrementing +/-x,+/2x,+/-4x etc. Any source of noise is possible as long, as there is 0 average phase error or latency added.

Digital clock phase or frequency error correction must be applied to the frequency at or above where you want stable by mixing at or above that frequency. If you mix at a lower frequency then time integration error correction is needed by accumulating error.

If you want to correct using PLL design then one uses a Vr controlled diode instead of one cap to reverse bias to modulate pF with DAC voltage from high series R-value.

Usually, the synchronized clock is inverted to the measured clock to allow a value to vary from the 50% of T=1/5 by the variation of the injected dither. This could be a sine quantized by any number of levels and determines how quickly you need to achieve your ppm or ppb error measurement.

Anecdotal

When I designed a PLL clock with 1e-12 stability for Doppler tracking, I used VLF signals since GPS was not invented yet and reduced the clocks to the lowest common frequency of 100Hz from multiple global radiated RF land sources. This enabled me to eliminate frequency error and measure phase shift from a moving receiver.

Then 20 years later in the 90's, I contributed to the design of a 1ppm TCXO for < $1 using my special 3rd order equations to correct AT- Xtal temperature error curves using a thermistor and tested varicaps binned for V/pF ratios and Xtals(crystals) tested at 24'C and 70'C in 10 seconds for the VCXO to tune 1GHz radios within 1ppm. It was just one tooth in a giant telemetry 2-way AMR network design we designed for 1 million clients sharing 6kHz ISM BW for automated meter reading.