What is the need for precharging in SRAM/ DRAM memory cell?

Question

Why is precharging so necessary while preforming read operation on SRAM/ DRAM cells?

For example in the SRAM 6T cell shown below,

Reading 0 requires bit line to discharge to 0; Reading 1 requires that bit line voltage is equivalent to logic '1' value.

Right?

So why can't this charge (in case of Q=1) occur via M4 and M6? i.e. why dont we consider M4-M6 as path strong enough to pull up the bit line?

Why do we rely on precharge value to give logic '1' on bit line?

Is it because NMOS M6 is a weak highpass?(due to the fact that NMOS is weak highpass)

Also, In case of precharging, is the precharge voltage = Vdd or Vdd/2 ?

Answer 1

The answers here are good regarding how in normal practice the bitlines will be charged to VDD/2. However that doesn't really answer the question, because it:

• does not apply all the time (depends on the cache requirements and process technologies. I have seen plenty of caches that precharge to VDD because at low voltage operation VDD/2 can be too risky)

• The 'canonical case' everyone learns first doesn't precharge to VDD/2, and this is the situation he is asking. There is still a good reason they go to VDD, though.

The main reason they charge the bitlines HIGH (in the circuit he is showing) and let them discharge is because the pass transistors are NMOS. This means they pass a very solid '0' but they pass a degraded '1'.

So rather than start the bitlines low and let them pull up through the NMOS (slower and weaker, can only pull to VSUPPLY-VTH), they will start the bitlines high and let them pull down through the NMOS (which can pull down more strongly, to a solid '0').

Another very good reason are the constraints on transistor sizing which must be met for proper writability/readability.

Read operation: M1 must be stronger than M5, so that the voltage divider formed between M5/M1 does not flip the bitnode.

Write operation: M2 must be weaker than M5, so that M5 can overcome the feedback loop when writing a '1'.

So, M1 > M5 > M2 (and M3 > M6 > M4). The PMOS are the weakest transistors in the whole cell, why use that to pull up?

On top of that, traditionally NMOS have been faster than PMOS. This is less true today in the lower process technologies (22nm, 14nm, 10nm, etc) but is still normally assumed.

Answer 2

Precharging is not intended to deal with the ability to source drive current into a bit line. Precharge is intended to minimize propagation delay time.

If there is no precharge, the maximum voltage swing in a readout is from a "0" to "1" (or vice versa), which happens in T01.

Precharging ensures that the bit line is driven to voltage midway between "0" and "1", so that when the actual cell is read out, the line need only be driven from the midway voltage to either "0" or "1". This results in about one half the transition time (1/2*T01), and results in a faster memory.

Answer 3

You can't drive a high-value through an NMOS switch. The output will stop rising fast once the output gets close to Vdd-Vt. Pre-charge allows the circuit to only have to drive a 0 value, which it can do well. I have attached a simple schematic to demonstrate the idea.

^{simulate this circuit – Schematic created using CircuitLab}

Answer 4

For DRAM, purpose of precharging is to close the current row and to allow activation of another row.

In the case when the same row cells are to be read, precharging can be done later when using Fast Page Mode DRAM.

Answer 5

Maybe you are referencing the wikipedia.

In SRAM page of wikipedia:

bit lines are relatively long and have large parasitic capacitance. To speed up reading, a more complex process is used in practice: The read cycle is started by precharging both bit lines BL and \$\overline{BL}\$, to high (logic 1) voltage. Then asserting the word line WL enables both the access transistors M5 and M6, which causes one bit line BL voltage to slightly drop.

So the precharge is to use more natural drop which will be done without any external forces or electromagnetism, instead of charging.

DRAM is just similar to what "AndyW" says (here only DRAM read will do precharge), but IMO its another function is to make 0.5V can change both upward and downward (0v can't go downward and \$V_{BL}\$ can't go upward) then it can be used in the positive feedback of the sense amplifier and then refresh the memory cells:

4. ... (e.g., 0.54 and 0.45 V in the two cases)
5. ... thereby amplifying the small voltage difference between the odd and even row bit-lines

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Hope my answer has no errors, if any, please point out and thanks.