What's the maximum number of lanes possible to use in a single PCI Express link? 16 or 32?

Question

I always thought that the maximum number of lanes for a PCI Express link was 16. The most powerful and expensive gaming GPUs never offer more lanes, and I have never seen a motherboard featuring a slot longer than 16 lanes. But is it really 32 lanes?

Support for 32 lanes

Reading the lengthy article on Wikipedia there are numerous quotes supporting up to 32 lanes:

The PCI Express link between two devices can vary in size from one to 32 lanes.

The PCI Express standard defines link widths of x1, x4, x8, x12, x16, and x32.

Consequently, a 32-lane PCIe connector (x32) can support an aggregate throughput of up to 16 GB/s.

A connection between any two PCIe devices is known as a link, and is built up from a collection of one or more lanes. All devices must minimally support single-lane (x1) link. Devices may optionally support wider links composed of 2, 4, 8, 12, 16, or 32 lanes.

Support for 16 lanes

But the same article also says that 16 is the maximum in many places:

Physical PCI Express links may contain from 1 to 16 lanes, more precisely 1, 4, 8 or 16 lanes.

Width in bits 1 per lane; 1–16 bonded lanes

A PCI Express card fits into a slot of its physical size or larger (with x16 as the largest used)

In real life

Meanwhile, a typical high performance graphics card is probably the most common mainstream expansion card to need a large amount of bandwidth. Enthusiasts pay several hundreds of dollars for these cards and often buy two or three. High-end consumer motherboards feature several PCIe x16 slots for this purpose. As we can see, there is obviously room for a longer connector on these cards:

A full-size ATX motherboard can also comfortably fit a connector that's twice as long.

There is also a continuously increasing demand on per-lane bandwidth. It tends to double for each new PCIe generation.

Question

With such a high demand of increased bandwidth, manufacturers competing to deliver motherboards with more and more PCIe x16 slots, millions of gamers paying hundreds of dollars each to get the absolute fastest graphics cards out there, why haven't I ever seen a PCIe x32 slot? Is there something in the standard preventing this?

Answer 1

32 lanes would mean a connector twice as long and would be a significant length of the width of the motherboard. It would severely restrict the PCB layout for devices below that connector as there would be less space to get around the x32 connector. It would make board design more difficult than the benefits it provides.

As a result you would either want it as the last or only PCIe connector. x16 is close to the existing PCI/AGP connectors and provides enough bandwidth for the use cases needed.

On top of that home CPUs have generally not had 32 or more PCIe lanes available directly from the chip. It has been, more often than not, 16 lanes available from the CPU, and another cluster of lanes provided by the motherboard chipset. More lanes means more pins from the CPU or chipset and larger chips as a result, and causes these devices to grow as a result.

Z170 Chipset:

Z370 Chipset:

There have always been other limits (bandwidth, CPU, etc) meaning that an x32 was only necessary once those limits improved, and at the same time the base PCIe specification was improved so that x16 moved up in speed as well. x32 would never really have given enough benefit to warrant the difficulties it would pose.

Answer 2

Yes, a Link Width of 32 lanes was legal / supported ... in PCI Express versions 1.0 through 5.0. It has not been often used by hardware vendors.
Another thing to consider is that when devices are using an active link width this wide, it suggests that processor core access to other Memory, data fabric, etc. would be similarly upsized - if the whole system is expected to leverage that greater I/O or accelerator capacity.
Starting in PCI Express 6.0 a link width of 32 lanes is no longer supported, or defined as valid by the PCI-SIG Base protocol Specification. x16 Link Width is the greatest defined link width to be supported by a PCIe 6.x component.